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公开(公告)号：US20230238455A1
公开(公告)日：2023-07-27
申请号：US18129095
申请日：2023-03-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Chang , Yao-Hsien Chung , Shih-Wei Su , Hao-Hsuan Chang , Ting-An Chien , Bin-Siang Tsai
IPC: H01L29/778 , H01L29/66 , H01L29/20
CPC classification number: H01L29/7786 , H01L29/66462 , H01L29/2003
Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is first subjected to the nitride treatment and is then subjected to the oxidation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.
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公开(公告)号：US11632889B2
公开(公告)日：2023-04-18
申请号：US17375021
申请日：2021-07-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Bin-Siang Tsai , Ya-Jyuan Hung , Chin-Chia Yang , Ting-An Chien
Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.
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公开(公告)号：US20210408368A1
公开(公告)日：2021-12-30
申请号：US16916037
申请日：2020-06-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Shih-Wei Su , Bin-Siang Tsai , Ting-An Chien
Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.
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公开(公告)号：US20210343789A1
公开(公告)日：2021-11-04
申请号：US17375021
申请日：2021-07-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Bin-Siang Tsai , Ya-Jyuan Hung , Chin-Chia Yang , Ting-An Chien
Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.
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公开(公告)号：US20210074917A1
公开(公告)日：2021-03-11
申请号：US16589148
申请日：2019-10-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Wei Su , Da-Jun Lin , Bin-Siang Tsai , Ya-Jyuan Hung , Ting-An Chien
Abstract: A method of forming a resistive random access memory cell includes the following steps. A first electrode layer, a blanket resistive switching material layer and a second electrode layer are formed on a layer sequentially. The second electrode layer is patterned to form a second electrode. The blanket resistive switching material layer is patterned to form a resistive switching material layer. An oxygen implanting process is performed to implant oxygen in two sidewall parts of the resistive switching material layer.
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Patent Agency Ranking
公开(公告)号：US12015076B2
公开(公告)日：2024-06-18
申请号：US18092916
申请日：2023-01-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Chang , Yao-Hsien Chung , Shih-Wei Su , Hao-Hsuan Chang , Da-Jun Lin , Ting-An Chien , Bin-Siang Tsai
IPC: H01L29/66 , H01L29/20 , H01L29/423 , H01L29/778
CPC classification number: H01L29/66462 , H01L29/2003 , H01L29/4236 , H01L29/42364 , H01L29/7786
Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed on the gate.
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公开(公告)号：US11762293B2
公开(公告)日：2023-09-19
申请号：US17316736
申请日：2021-05-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hao-Hsuan Chang , Da-Jun Lin , Yao-Hsien Chung , Ting-An Chien , Bin-Siang Tsai , Chih-Wei Chang , Shih-Wei Su , Hsu Ting , Sung-Yuan Tsai
CPC classification number: G03F7/0755 , G03F7/2043 , C23C16/345
Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.
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公开(公告)号：US20230163207A1
公开(公告)日：2023-05-25
申请号：US17834936
申请日：2022-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Chang , Da-Jun Lin , Yao-Hsien Chung , Shih-Wei Su , Hao-Hsuan Chang , Ting-An Chien , Bin-Siang Tsai
IPC: H01L29/778 , H01L29/20 , H01L29/66
CPC classification number: H01L29/7786 , H01L29/2003 , H01L29/66462
Abstract: The invention provides a semiconductor structure, which comprises a GaN gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer on the gallium nitride layer, a polarization boost layer on and in direct contact with the aluminum gallium nitride layer, and a gate liner layer on the polarization boost layer.
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公开(公告)号：US11495737B2
公开(公告)日：2022-11-08
申请号：US16916037
申请日：2020-06-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Shih-Wei Su , Bin-Siang Tsai , Ting-An Chien
Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.
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公开(公告)号：US20220165866A1
公开(公告)日：2022-05-26
申请号：US17143135
申请日：2021-01-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Chang , Yao-Hsien Chung , Shih-Wei Su , Hao-Hsuan Chang , Da-Jun Lin , Ting-An Chien , Bin-Siang Tsai
IPC: H01L29/66 , H01L29/20 , H01L29/778
Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate.
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