公开(公告)号：US11355619B2

公开(公告)日：2022-06-07

申请号：US16836872

申请日：2020-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/768 ,  H01L29/417 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.

公开(公告)号：US20200185525A1

公开(公告)日：2020-06-11

申请号：US16792120

申请日：2020-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yeh Huang ,  Te-Chang Hsu ,  Chun-Jen Huang ,  Che-Hsien Lin ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/10 ,  H01L29/51 ,  H01L21/768 ,  H01L29/04 ,  H01L29/49 ,  H01L21/324

Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.

公开(公告)号：US10651290B2

公开(公告)日：2020-05-12

申请号：US16239470

申请日：2019-01-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/768 ,  H01L29/417 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer around the gate structure, performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer, and then performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.

公开(公告)号：US20190140077A1

公开(公告)日：2019-05-09

申请号：US16239470

申请日：2019-01-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC: H01L29/66 ,  H01L21/3115 ,  H01L21/3105

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer around the gate structure, performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer, and then performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.

公开(公告)号：US20190103492A1

公开(公告)日：2019-04-04

申请号：US15722801

申请日：2017-10-02

Applicant: United Microelectronics Corp.

Inventor： Cheng-Pu Chiu ,  Pei-Yu Chen ,  Shih-Min Lu ,  Ming-Yueh Tsai ,  Yung-Sung Lin ,  Te-Chang Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng ,  Sheng-Chen Chung ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66 ,  H01L21/02

Abstract: A method for forming epitaxial material on base material includes forming a stress cap layer on a base layer of a first semiconductor material. Then, a stress is induced on the base layer, wherein the stress is a tensile stress or a compressive stress. The stress cap layer is removed. An epitaxial layer of a second semiconductor material is formed on the base layer, wherein the second semiconductor material is different from the first semiconductor material.

公开(公告)号：US10249729B1

公开(公告)日：2019-04-02

申请号：US15832696

申请日：2017-12-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Hsien Chen ,  Chun-Chia Chen ,  Yao-Jhan Wang ,  Chih-wei Yang ,  Te-Chang Hsu

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08

Abstract: A method for fabricating a semiconductor device. After forming SiGe epitaxial layer within the Core_p region, the hard mask is removed. A contact etch stop layer (CESL) is deposited on the composite spacer structure and the epitaxial layer. An ILD layer is deposited on the CESL. The ILD layer is polished to expose a top surface of the dummy gate. The dummy gate and a first portion of the first nitride-containing layer of the composite spacer structure are removed, thereby forming a gate trench and exposing the first gate dielectric layer. The first gate dielectric layer is removed from the gate trench, and a second portion of the first nitride-containing layer and the oxide layer are removed from the composite spacer structure, while leaving the second nitride-containing layer intact.