公开(公告)号：US20190103492A1

公开(公告)日：2019-04-04

申请号：US15722801

申请日：2017-10-02

Applicant: United Microelectronics Corp.

Inventor： Cheng-Pu Chiu ,  Pei-Yu Chen ,  Shih-Min Lu ,  Ming-Yueh Tsai ,  Yung-Sung Lin ,  Te-Chang Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng ,  Sheng-Chen Chung ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66 ,  H01L21/02

Abstract: A method for forming epitaxial material on base material includes forming a stress cap layer on a base layer of a first semiconductor material. Then, a stress is induced on the base layer, wherein the stress is a tensile stress or a compressive stress. The stress cap layer is removed. An epitaxial layer of a second semiconductor material is formed on the base layer, wherein the second semiconductor material is different from the first semiconductor material.

公开(公告)号：US10217866B2

公开(公告)日：2019-02-26

申请号：US15696201

申请日：2017-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/82

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.

公开(公告)号：US20190043760A1

公开(公告)日：2019-02-07

申请号：US16132460

申请日：2018-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  An-Chi Liu ,  Nan-Yuan Huang ,  Yu-Chih Su ,  Cheng-Pu Chiu ,  Tien-Shan Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/762

Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.

公开(公告)号：US20240413017A1

公开(公告)日：2024-12-12

申请号：US18220839

申请日：2023-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Ya-Ting Hu ,  Wei-Che Chen ,  Chang-Yih Chen ,  Kun-Szu Tseng ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, forming fin-shaped structures on the LV region, forming an insulating layer between the fin-shaped structures, forming a hard mask on the LV region, and then performing a thermal oxidation process to form a gate dielectric layer on the MV region. Preferably, a hump is formed on the substrate surface of the MV region after the hard mask is removed, in which the hump further includes a first hump adjacent to one side of the substrate on the MV region and a second hump adjacent to another side of the substrate on the MV region.

公开(公告)号：US20190148550A1

公开(公告)日：2019-05-16

申请号：US16244076

申请日：2019-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/7846 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.

公开(公告)号：US20250015186A1

公开(公告)日：2025-01-09

申请号：US18227299

申请日：2023-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chun Lee ,  Chih-Yi Wang ,  Wei-Che Chen ,  Ya-Ting Hu ,  Yao-Jhan Wang ,  Kun-Szu Tseng ,  Feng-Yun Cheng ,  Shyan-Liang Chou

IPC: H01L29/78 ,  H01L25/16

Abstract: The invention provides a semiconductor structure, which comprises a middle/high voltage device region and a low voltage device region, a plurality of fin structures disposed in the low voltage device region, and a protruding part located at a boundary Between the middle/high voltage device region and the low voltage device region. A top surface of the protruding part is flat, and the top surface of the protruding part is aligned with a flat top surface of the middle/high voltage device region.

公开(公告)号：US20240363430A1

公开(公告)日：2024-10-31

申请号：US18203654

申请日：2023-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Wei-Che Chen ,  Hung-Chun Lee ,  Yun-Yang He ,  Wei-Hao Chang ,  Chang-Yih Chen ,  Kun-Szu Tseng ,  Yao-Jhan Wang ,  Ying-Hsien Chen

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an active region as the substrate includes a medium-voltage (MV) region and a low-voltage (LV) region, forming a first divot adjacent to one side of the active region, forming a second divot adjacent to another side of the active region, forming a first liner in the first divot and the second divot and on the substrate of the MV region and LV region, forming a second liner on the first liner, and then removing the second liner, the first liner, and the substrate on the LV region for forming a fin-shaped structure.

公开(公告)号：US20210035977A1

公开(公告)日：2021-02-04

申请号：US17075729

申请日：2020-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Tien-Shan Hsu ,  Cheng-Pu Chiu ,  Yao-Jhan Wang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/26

Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.

公开(公告)号：US10686079B1

公开(公告)日：2020-06-16

申请号：US16243014

申请日：2019-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Cheng-Pu Chiu ,  Huang-Ren Wei ,  Tien-Shan Hsu ,  Chi-Sheng Tseng ,  Yao-Jhan Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417 ,  H01L21/3213 ,  H01L21/8234

Abstract: A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.

公开(公告)号：US10446682B2

公开(公告)日：2019-10-15

申请号：US16244076

申请日：2019-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.