公开(公告)号：US20240339501A1

公开(公告)日：2024-10-10

申请号：US18143095

申请日：2023-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Hsien Lin ,  Te-Chang Hsu ,  Chun-Jen Huang ,  Chun-Chia Chen

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a fin-shaped structure on the substrate, forming a gate structure on the fin-shaped structure, removing the fin-shaped structure to form a recess, forming a first epitaxial layer in the recess adjacent to the gate structure, and then forming a second epitaxial layer on the first epitaxial layer. Preferably, the semiconductor device further includes a first protrusion on one side of the first epitaxial layer and a second protrusion on another side of the first epitaxial layer.

公开(公告)号：US20240071818A1

公开(公告)日：2024-02-29

申请号：US17950120

申请日：2022-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Wei Chi ,  Te-Chang Hsu ,  Yao-Jhan Wang ,  Meng-Yun Wu ,  Chun-Jen Huang

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/76829 ,  H01L21/02041 ,  H01L21/02293 ,  H01L21/02529 ,  H01L21/02532 ,  H01L29/66795

Abstract: A semiconductor device and method of fabricating the same include a substrate, a first epitaxial layer, a first protection layer, and a contact etching stop layer. The substrate includes a PMOS transistor region, and the first epitaxial layer is disposed on the substrate, within the PMOS transistor region. The first protection layer is disposed on the first epitaxial layer, covering surfaces of the first epitaxial layer. The contact etching stop layer is disposed on the first protection layer and the substrate, wherein a portion of the first protection layer is exposed from the contact etching stop layer.

公开(公告)号：US10283415B2

公开(公告)日：2019-05-07

申请号：US16132460

申请日：2018-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  An-Chi Liu ,  Nan-Yuan Huang ,  Yu-Chih Su ,  Cheng-Pu Chiu ,  Tien-Shan Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/762

Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.

公开(公告)号：US10211107B1

公开(公告)日：2019-02-19

申请号：US15700175

申请日：2017-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Tien-Shan Hsu ,  Yu-Chih Su ,  Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Te-Chang Hsu ,  Chin-Yang Hsieh ,  An-Chi Liu ,  Kuan-Lin Chen ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/762

Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.

公开(公告)号：US10109531B1

公开(公告)日：2018-10-23

申请号：US15616936

申请日：2017-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  An-Chi Liu ,  Nan-Yuan Huang ,  Yu-Chih Su ,  Cheng-Pu Chiu ,  Tien-Shan Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/762

Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A topmost portion of the first bump is lower than the base, and a width of the first bump is larger than a width of each of the fin shaped structures.

公开(公告)号：US10892365B2

公开(公告)日：2021-01-12

申请号：US16792120

申请日：2020-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yeh Huang ,  Te-Chang Hsu ,  Chun-Jen Huang ,  Che-Hsien Lin ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L29/10 ,  H01L29/161 ,  H01L29/51 ,  H01L29/49 ,  H01L21/768 ,  H01L21/324

Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.

公开(公告)号：US20200279917A1

公开(公告)日：2020-09-03

申请号：US16878542

申请日：2020-05-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Che-Hsien Lin ,  Cheng-Yeh Huang ,  Chun-Jen Huang ,  Yu-Chih Su ,  Yao-Jhan Wang

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311 ,  H01L29/78 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.

公开(公告)号：US20190058050A1

公开(公告)日：2019-02-21

申请号：US15710820

申请日：2017-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang ,  Chun-Jen Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

公开(公告)号：US10037915B1

公开(公告)日：2018-07-31

申请号：US15700171

申请日：2017-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L29/78

CPC classification number: H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fabricating method of a semiconductor structure includes providing a substrate divided into a dense region and an isolated region, wherein a first gate structure is disposed within the dense region, and a second gate structure is disposed within the isolated region. Then, a first material layer is formed to cover the first gate structure, the second gate structure and the substrate. Later, a second material layer is formed to cover the first material layer. After that, the second material layer within the dense region is entirely removed. Subsequently, a third material layer is formed to cover the isolated region and the dense region. Next, the substrate is etched to forma first recess at two sides of the first gate structure, and a second recess at two sides of the second gate structure. Finally, an epitaxial layer is formed to fill the first recess and the second recess.

公开(公告)号：US11742412B2

公开(公告)日：2023-08-29

申请号：US16985242

申请日：2020-08-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang ,  Chun-Jen Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/16 ,  H01L29/24 ,  H01L29/161

CPC classification number: H01L29/6656 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823821 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/1608 ,  H01L29/24 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.