公开(公告)号：US20250040198A1

公开(公告)日：2025-01-30

申请号：US18917997

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first fin-shaped structure between the first epitaxial layer and the substrate, and a first contact plug between the first epitaxial layer and the second epitaxial layer. Preferably, the first gate structure includes a gate dielectric layer, top surfaces of the gate dielectric layer and the first fin-shaped structure are coplanar, and a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug.

公开(公告)号：US20230395657A1

公开(公告)日：2023-12-07

申请号：US18235358

申请日：2023-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US10217866B2

公开(公告)日：2019-02-26

申请号：US15696201

申请日：2017-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/82

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.

公开(公告)号：US20190043760A1

公开(公告)日：2019-02-07

申请号：US16132460

申请日：2018-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  An-Chi Liu ,  Nan-Yuan Huang ,  Yu-Chih Su ,  Cheng-Pu Chiu ,  Tien-Shan Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/762

Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.

公开(公告)号：US12148796B2

公开(公告)日：2024-11-19

申请号：US18235358

申请日：2023-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US20190148550A1

公开(公告)日：2019-05-16

申请号：US16244076

申请日：2019-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/7846 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.

公开(公告)号：US20220165844A1

公开(公告)日：2022-05-26

申请号：US17670528

申请日：2022-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US20190103492A1

公开(公告)日：2019-04-04

申请号：US15722801

申请日：2017-10-02

Applicant: United Microelectronics Corp.

Inventor： Cheng-Pu Chiu ,  Pei-Yu Chen ,  Shih-Min Lu ,  Ming-Yueh Tsai ,  Yung-Sung Lin ,  Te-Chang Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng ,  Sheng-Chen Chung ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66 ,  H01L21/02

Abstract: A method for forming epitaxial material on base material includes forming a stress cap layer on a base layer of a first semiconductor material. Then, a stress is induced on the base layer, wherein the stress is a tensile stress or a compressive stress. The stress cap layer is removed. An epitaxial layer of a second semiconductor material is formed on the base layer, wherein the second semiconductor material is different from the first semiconductor material.

公开(公告)号：US11569235B2

公开(公告)日：2023-01-31

申请号：US17075729

申请日：2020-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Tien-Shan Hsu ,  Cheng-Pu Chiu ,  Yao-Jhan Wang

IPC: H01L21/308 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/26

Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.

公开(公告)号：US20190080968A1

公开(公告)日：2019-03-14

申请号：US15700175

申请日：2017-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Tien-Shan Hsu ,  Yu-Chih Su ,  Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Te-Chang Hsu ,  Chin-Yang Hsieh ,  An-Chi Liu ,  Kuan-Lin Chen ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/762

Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.