公开(公告)号：US10133700B2

公开(公告)日：2018-11-20

申请号：US15389517

申请日：2016-12-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa Canac ,  James R. Lundberg

IPC: G06F13/42 ,  G06F1/12 ,  G11C8/18 ,  G11C7/10

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus, the apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal, and is configured to generate a first value on a lag bus that indicates the time. The bit lag control element has delay lock control that is configured to select one of a plurality of successively delayed versions of the lag pulse signal that coincides with the assertion the replicated strobe signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the lag pulse signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions comprises inputs to the mux, and where the plurality of successively delayed versions comprises outputs a first plurality of series-coupled matched inverter pairs. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the time.

公开(公告)号：US10079046B2

公开(公告)日：2018-09-18

申请号：US15389763

申请日：2016-12-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa Canac ,  James R. Lundberg

IPC: G06F1/12 ,  G11C7/10 ,  G06F13/42 ,  G11C8/18 ,  G06F13/362 ,  G06F13/40

CPC classification number: G11C7/1072 ,  G06F1/12 ,  G06F13/3625 ,  G06F13/4068 ,  G06F13/4217 ,  G06F13/4243 ,  G11C8/18

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a first signal, and is configured to generate a second signal, where the replica radial distribution element comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The bit lag control element has delay lock control and a gray encoder. The delay lock control is configured to select one of a plurality of successively delayed versions of the first signal that coincides with the assertion of the second signal, where the delay lock control selects the one of a plurality of successively delayed versions of the first signal by incrementing and decrementing bus states of select inputs on a first mux, and where the plurality of successively delayed versions of the first signal comprises inputs to the first mux, and where the plurality of successively delayed versions comprises outputs of a first plurality of series-coupled matched inverter pairs. The gray encoder is configured to gray encode the propagation time to generate the value on the lag bus. The synchronous lag receiver is configured to receive one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time. The synchronous lag receiver includes a second plurality of series-coupled matched inverter pairs, a second mux, and a bit receiver. The second plurality of series-coupled matched inverter pairs is configured to generate successively delayed versions of the data bit. The second mux is coupled to the second plurality of series-coupled matched inverter pairs, is configured to receive the value on the lag bus, and is configured to select one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver is configured to receive the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and is configured to register the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of radially distributed strobe signals.

公开(公告)号：US09552320B2

公开(公告)日：2017-01-24

申请号：US13747038

申请日：2013-01-22

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F13/42

CPC classification number: G06F13/4243 ,  G06F1/12 ,  G06F13/4217 ,  G11C7/1072 ,  G11C8/18

Abstract: A method that compensates for misalignment on a synchronous data bus. The method includes: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe, receiving a lag pulse signal, and generating a replicated strobe signal by employing the replicated propagation path loads lengths, and buffering; measuring the time between assertion of the lag pulse signal and assertion of the replicated strobe signal; on a lag bus, generating a value that indicates the time; within a synchronous lag receiver, receiving a first one of a plurality of radially distributed strobes and a data bit, and delaying registering of the data bit by the time.

Abstract translation: 补偿同步数据总线上的未对准的方法。 该方法包括：复制用于选通的径向分布网络的传播路径长度，负载和缓冲，接收延迟脉冲信号，以及通过采用复制的传播路径负载长度和缓冲来产生复制的选通信号; 测量滞后脉冲信号的断言与复制的选通信号的断言之间的时间; 在滞后总线上产生一个表示时间的值; 在同步延迟接收器内，接收多个径向分布的选通信号中的第一个选通信号和数据位，并延迟数据位的记录。

公开(公告)号：US20140361823A1

公开(公告)日：2014-12-11

申请号：US14202288

申请日：2014-03-10

Applicant: VIA TECHNOLOGIES, INC.

Inventor： James R. Lundberg

IPC: H03K3/012

CPC classification number: H03K3/012 ,  G06F1/26 ,  G06F1/3243 ,  H03K19/0008 ,  Y02D10/152

Abstract: A system which may be implemented on an integrated circuit including a global supply bus, a gated supply bus, a functional circuit receiving voltage from the gated supply bus, and a digital power gating system. The digital power gating system includes gating devices, a power gating control system, and a global control adjuster. The gating devices are coupled between the global and gated supply buses and are controlled by a digital control value. The power gating control system performs power gating by successively adjusting the digital control value to reduce a voltage of the gated supply bus to a state retention voltage level. The global control adjuster performs a global adjustment of the digital control value to increase the voltage of the gated supply bus to prevent it from falling below the state retention voltage level in response to an impending change of a voltage of the global supply bus.

Abstract translation: 可以在包括全局电源总线，门控电源总线，从门控电源总线接收电压的功能电路以及数字电源门控系统的集成电路上实现的系统。 数字电源门控系统包括门控设备，电源门控控制系统和全局控制调节器。 门控设备耦合在全局和门控供电总线之间，并由数字控制值控制。 电源门控控制系统通过连续调整数字控制值来执行电源门控，以将门控电源总线的电压降低到状态保持电压电平。 全局控制调节器执行数字控制值的全局调整，以增加门控电源总线的电压，以防止其响应于全局电源总线的电压即将发生变化而降低到状态保持电压电平以下。

公开(公告)号：US08878580B1

公开(公告)日：2014-11-04

申请号：US14030560

申请日：2013-09-18

Applicant: VIA Technologies, Inc.

Inventor： Darius D. Gaskins ,  James R. Lundberg

IPC: H03L7/06

CPC classification number: H03L7/22

Abstract: A clock system receiving a reference clock signal via an alignment location and developing a functional clock signal provided to a functional circuit via a clock path. The clock system includes a low bandwidth PLL, a high bandwidth PLL, and a delay path. The low bandwidth PLL receives the reference clock signal and a feedback clock signal and provides a filtered clock signal. The high bandwidth PLL receives the filtered clock signal and provides the functional clock signal, and has a feedback input coupled to its output via a local feedback path. The delay path is coupled between the output of the low bandwidth PLL and the alignment location to provide the feedback clock signal to the low bandwidth PLL. The delay and clock paths are substantially matched. The bandwidths of the low and high bandwidth PLLs may be individually configured to reduce both input jitter and internal jitter, respectively.

Abstract translation: 时钟系统经由对准位置接收参考时钟信号，并且经由时钟路径开发提供给功能电路的功能时钟信号。 时钟系统包括低带宽PLL，高带宽PLL和延迟路径。 低带宽PLL接收参考时钟信号和反馈时钟信号，并提供滤波后的时钟信号。 高带宽PLL接收经滤波的时钟信号并提供功能时钟信号，并具有通过本地反馈路径耦合到其输出的反馈输入。 延迟路径耦合在低带宽PLL的输出和对准位置之间，以将反馈时钟信号提供给低带宽PLL。 延迟和时钟路径基本匹配。 低带宽和高带宽PLL的带宽可以单独配置为分别减少输入抖动和内部抖动。