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    Dynamic Reconfiguration of Multi-core Processor
    1.
    发明申请
    Dynamic Reconfiguration of Multi-core Processor 审中-公开

    公开(公告)号：US20190095216A1

    公开(公告)日：2019-03-28

    申请号：US16203819

    申请日：2018-11-29

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Terry Parks ,  Darius D. Gaskins

    IPC: G06F9/38 ,  G06F9/4401 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/30 ,  G06F12/0808 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F12/0875 ,  G06F13/364 ,  G06F21/57 ,  H04L9/08 ,  G06F21/53 ,  H01L21/66

    Abstract: A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

    Domain-differentiated power state coordination system
    3.
    发明授权
    Domain-differentiated power state coordination system 有权

    公开(公告)号：US10409347B2

    公开(公告)日：2019-09-10

    申请号：US16191691

    申请日：2018-11-15

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Darius D. Gaskins

    IPC: G06F1/26 ,  G06F1/3287 ,  G06F1/24 ,  G06F13/36 ,  G06F15/163 ,  G06F9/30 ,  G06F9/50 ,  G06F9/445 ,  G06F15/82 ,  G06F1/3234 ,  G06F11/36 ,  G06F11/14

    Abstract: A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core's target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.

    Domain-differentiated power state coordination system
    5.
    发明授权
    Domain-differentiated power state coordination system 有权

    公开(公告)号：US10175732B2

    公开(公告)日：2019-01-08

    申请号：US14980194

    申请日：2015-12-28

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. Glenn Henry ,  Darius D. Gaskins

    IPC: G06F1/26 ,  G06F1/32 ,  G06F1/24 ,  G06F13/36 ,  G06F15/163 ,  G06F9/30 ,  G06F9/50 ,  G06F9/445 ,  G06F15/82 ,  G06F11/36 ,  G06F11/14

    Abstract: A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core's target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.

    Power state synchronization in a multi-core processor
    6.
    发明授权
    Power state synchronization in a multi-core processor 有权
    多核处理器中的电源状态同步

    公开(公告)号：US09009512B2

    公开(公告)日：2015-04-14

    申请号：US14172373

    申请日：2014-02-04

    Applicant: VIA Technologies, Inc.

    Inventor： G. Glenn Henry ,  Darius D. Gaskins

    IPC: G06F1/32 ,  G06F1/26 ,  G06F9/50

    CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22

    Abstract: A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications.

    Abstract translation: 多核处理器包括分布在每个核心中的微码，使得每个核心能够参与去集中的核心间状态发现过程。 在相关的微代码实现方法中，多核处理器的状态由参与去集中式核心状态发现过程的至少两个核心发现。 通过在每个参与核心上执行的微代码和通过边带非系统总线通信线路在核心之间交换的信号的组合来执行核心间状态发现处理。 发现过程不受任何集中式非核心逻辑的介入。 适用的可发现状态包括目标和复合功率状态，是否启用了多少核心，启用各种资源的可用性和分布，以及核心的分层结构和协调系统。 核心状态发现过程可以根据涉及链接的核心间通信的各种分层协调系统来执行。

    Distributed management of a shared clock source to a multi-core microprocessor
    9.
    发明授权
    Distributed management of a shared clock source to a multi-core microprocessor 有权
    将共享时钟源分布式管理到多核微处理器

    公开(公告)号：US09298212B2

    公开(公告)日：2016-03-29

    申请号：US14143666

    申请日：2013-12-30

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Darius D. Gaskins ,  G. Glenn Henry

    IPC: G06F1/06 ,  G06F1/32

    CPC classification number: G06F1/06 ,  G06F1/3296 ,  Y02D10/172

    Abstract: Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores.

    Abstract translation: 微处理器具有分散逻辑和相关联的方法，用于将功率相关的操作状态（例如期望的电压和频率比）指示给共享的微处理器功率资源，例如电压调节器模块（VRM）和锁相环（PLL）。 每个核心被配置为产生一个值以指示所述核心的期望操作状态。 每个核心还被配置为从彼此分配可用资源的核心接收相应的值，并且计算与共享可应用资源的每个核心的最小需求兼容的复合值。 每个核心还被配置为基于是否将核心指定为主核以有条件地将核心的复合值驱动到适用的资源，以便控制或协调适用的资源。 复合值被提供给可应用的共享资源，而不使用多个核之外的任何活动逻辑。

    Multi-core dies produced by reticle set modification
    10.
    发明授权
    Multi-core dies produced by reticle set modification 有权
    通过掩模版修改生产的多芯模具

    公开(公告)号：US09099549B2

    公开(公告)日：2015-08-04

    申请号：US14094206

    申请日：2013-12-02

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Darius D. Gaskins

    IPC: H01L21/78 ,  G03F1/00

    CPC classification number: H01L21/78 ,  G03F1/00

    Abstract: A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus.

    Abstract translation: 设计用于制造具有有限数量的芯的模具的第一掩模版组被修改成适于制造具有至少两倍的芯的至少一些裸片的第二掩模版集合。 第一个标线组定义划线以分离原始定义的模具。 从相邻但最初明确定义的模具的对中移除至少一个划线。 核心间通信线被定义为连接相邻的核心，其被配置为使得相邻的核心在操作期间进行通信，而不连接到所产生的更多核心的芯片的任何物理输入/输出着陆焊盘，其不会通过 核心间通信线从P型芯片上卸下。 核心间通信线可以用于电源管理协调目的或绕过外部处理器总线。

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