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    COHERENCE-BASED DYNAMIC CODE REWRITING, TRACING AND CODE COVERAGE
    22.
    发明申请
    COHERENCE-BASED DYNAMIC CODE REWRITING, TRACING AND CODE COVERAGE 有权

    公开(公告)号：US20230028825A1

    公开(公告)日：2023-01-26

    申请号：US17531582

    申请日：2021-11-19

    Applicant: VMware, Inc.

    Inventor： Irina CALCIU ,  Andreas NOWATZYK ,  Pratap SUBRAHMANYAM

    IPC: G06F8/656 ,  G06F9/38 ,  G06F9/30 ,  G06F9/455 ,  G06F13/16

    Abstract: A device tracks accesses to pages of code executed by processors and modifies a portion of the code without terminating the execution of the code. The device is connected to the processors via a coherence interconnect and a local memory of the device stores the code pages. As a result, any requests to access cache lines of the code pages made by the processors will be placed on the coherence interconnect, and the device is able to track any cache-line accesses of the code pages by monitoring the coherence interconnect. In response to a request to read a cache line having a particular address, a modified code portion is returned in place of the code portion stored in the code pages.

    FAILURE-ATOMIC LOGGING FOR PERSISTENT MEMORY SYSTEMS WITH CACHE-COHERENT FPGAS
    23.
    发明申请
    FAILURE-ATOMIC LOGGING FOR PERSISTENT MEMORY SYSTEMS WITH CACHE-COHERENT FPGAS 审中-公开

    公开(公告)号：US20200242036A1

    公开(公告)日：2020-07-30

    申请号：US16256571

    申请日：2019-01-24

    Applicant: VMware, Inc.

    Inventor： Aasheesh KOLLI ,  Irina CALCIU ,  Jayneel GANDHI ,  Pratap SUBRAHMANYAM

    IPC: G06F12/0831 ,  G06F12/109 ,  G06F12/0817 ,  G06F11/07 ,  G06F9/50

    Abstract: Disclosed is a technique in which an application can record changes it makes to physical memory. In the technique, the application specifies a virtual memory region which is converted to a plurality of cache lines, each of which is monitored for changes by a device connected to a coherence interconnect coupled to the processor caches. The application sends a start signal to start the logging process and an end signal to stop the process. During the logging process, when a change occurs to one of the cache lines, an undo entry corresponding to the change is created and entered into a transaction log residing in persistent memory. The transaction log containing the undo entries makes the set of changes recorded in the transaction log atomic. If a failure occurs, the recorded changes can be undone as if they never occurred.

    FAILURE-ATOMIC PERSISTENT MEMORY LOGGING USING BINARY TRANSLATION
    24.
    发明申请
    FAILURE-ATOMIC PERSISTENT MEMORY LOGGING USING BINARY TRANSLATION 审中-公开

    公开(公告)号：US20200241978A1

    公开(公告)日：2020-07-30

    申请号：US16256567

    申请日：2019-01-24

    Applicant: VMware, Inc.

    Inventor： Aasheesh KOLLI ,  Irina CALCIU ,  Jayneel GANDHI ,  Pratap SUBRAHMANYAM

    IPC: G06F11/14

    Abstract: A module for rewriting application code as a failure-atomic transaction is disclosed. An application delineates a code fragment that is to become a failure-atomic transaction by writing a tx_begin( ) and tx_end( ) functions into its code. A module detects the tx_begin( ) and tx_end( ) functions and rewrites the code fragment as a failure-atomic transaction. The rewritten code is then available to be executed by the application. The rewritten code stores values and locations of stores to persistent memory locations so that the transaction can be either undone or redone in the case of an application error or a power failure. If the transaction is an undo type of transaction, the application can be rolled back to a state prior to the failure. If the transaction is a redo type of transaction, the application can be advanced to a correct state after the error.

    USING CACHE COHERENT FPGAS TO ACCELERATE REMOTE ACCESS
    25.
    发明申请
    USING CACHE COHERENT FPGAS TO ACCELERATE REMOTE ACCESS 审中-公开

    公开(公告)号：US20200034294A1

    公开(公告)日：2020-01-30

    申请号：US16048186

    申请日：2018-07-27

    Applicant: VMware, Inc.

    Inventor： Irina CALCIU ,  Jayneel GANDHI ,  Aasheesh KOLLI ,  Pratap SUBRAHMANYAM

    IPC: G06F12/0815 ,  G06F12/0862 ,  G06F12/1009 ,  G06F9/455

    Abstract: Disclosed are embodiments for running an application on a local processor when the application is dependent on pages not locally present but contained in a remote host. The system is informed that the pages on which the application depends are locally present. While running, the application encounters a cache miss and a cache line satisfying the miss from the remote host is obtained and provided to the application. Alternatively, the page containing the cache line satisfying the miss is obtained and the portion of the page not including the cache line is stored locally while the cache line is provided to the application. The cache miss is discovered by monitoring coherence events on a coherence interconnect connected to the local processor. In some embodiments, the cache misses are tracked and provide a way to predict a set of pages to be pre-fetched in anticipation of the next cache misses.

    SMART PREFETCHING FOR REMOTE MEMORY
    28.
    发明申请
    SMART PREFETCHING FOR REMOTE MEMORY 有权

    公开(公告)号：US20230004497A1

    公开(公告)日：2023-01-05

    申请号：US17872744

    申请日：2022-07-25

    Applicant: VMware, Inc.

    Inventor： Irina CALCIU ,  Andreas NOWATZYK ,  Isam Wadih AKKAWI ,  Venkata Subhash Reddy PEDDAMALLU ,  Pratap SUBRAHMANYAM

    IPC: G06F12/0862

    Abstract: A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.

    ACCELERATING REPLICATION OF PAGE TABLES FOR MULTI-SOCKET MACHINES
    29.
    发明申请
    ACCELERATING REPLICATION OF PAGE TABLES FOR MULTI-SOCKET MACHINES 审中-公开

    公开(公告)号：US20200233804A1

    公开(公告)日：2020-07-23

    申请号：US16255432

    申请日：2019-01-23

    Applicant: VMware, Inc.

    Inventor： Jayneel GANDHI ,  Pratap SUBRAHMANYAM ,  Irina CALCIU ,  Aasheesh KOLLI

    IPC: G06F12/0853 ,  G06F12/1045 ,  G06F12/1009 ,  G06F12/0804 ,  G06F12/0817

    Abstract: Described herein is a method for tracking changes made by an application. Embodiments include determining, by a processor, a write-back of a cache line from a hardware unit associated with a socket of a plurality of sockets to a page table entry of a page table in a memory location associated with the processor. Embodiments include adding, by the processor, the cache line to a list of dirty cache lines. Embodiments include, for each respective cache line in the list of dirty cache lines, identifying, by the processor, a memory location associated with a respective socket of the plurality of sockets corresponding to the respective cache line and updating, by the processor, an entry of a page table replica at the memory location based on the respective cache line.

    USING CACHE COHERENT FPGAS TO ACCELERATE POST-COPY MIGRATION
    30.
    发明申请
    USING CACHE COHERENT FPGAS TO ACCELERATE POST-COPY MIGRATION 审中-公开

    公开(公告)号：US20200034176A1

    公开(公告)日：2020-01-30

    申请号：US16048183

    申请日：2018-07-27

    Applicant: VMware, Inc.

    Inventor： Irina CALCIU ,  Jayneel GANDHI ,  Aasheesh KOLLI ,  Pratap SUBRAHMANYAM

    IPC: G06F9/455 ,  G06F12/0862 ,  G06F12/0815 ,  G06F15/173

    Abstract: Disclosed are embodiments for migrating a virtual machine (VM) from a source host to a destination host while the virtual machine is running on the destination host. The system includes an RDMA facility connected between the source and destination hosts and a device coupled to a local memory, the local memory being responsible for memory pages of the VM instead of the source host. The device is configured to copy pages of the VM to the destination host and to maintain correct operation of the VM by monitoring coherence events, such as a cache miss, caused by the virtual machine running on the destination host. The device services these cache misses using the RDMA facility and copies the cache line satisfying the cache miss to the CPU running the VM. The device also tracks the cache misses to create an access pattern that it uses to predict future cache misses.

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