-
21.发明授权
公开(公告)号：US5790870A
公开(公告)日：1998-08-04
申请号：US573030
申请日：1995-12-15
CPC分类号： G06F11/0745 , G06F11/0793
摘要： An apparatus for handling bus error signals is provided for a computer having a processor, an interrupt controller, a first PCI bus with first PERR# and SERR# signals, and a second PCI bus with second PERR# and SERR# signals. The apparatus has a buffer with an input connected to ground, an enable input connected to the second SERR# signal, and an output connected to the first SERR# signal. When the second SERR# signal is asserted, the first SERR# signal is also asserted via the buffer and is provided to one input of the interrupt controller. In an alternate embodiment, the buffer enable input is connected to the first SERR# signal and the buffer output connected to the second SERR# signal. The apparatus also receives the first and second PERR# signals and logically ORs the signals together to generate a combined PERR# signal. The combined PERR# signal is presented to a register which is clocked by the PCI system clock to synchronize the combined PERR# signal to the PCI clock before presenting the PERR# signal to a second input of the interrupt controller. The interrupt controller generates an interrupt to the processor and causes the processor to poll devices to identify the board that might have caused the error and to take a corrective action.
摘要翻译： 为具有处理器，中断控制器，具有第一PERR＃和SERR＃信号的第一PCI总线以及具有第二PERR＃和SERR＃信号的第二PCI总线的计算机提供一种用于处理总线错误信号的装置。 该装置具有连接到地的输入的缓冲器，连接到第二SERR＃信号的使能输入和连接到第一SERR＃信号的输出。 当第二个SERR＃信号有效时，第一个SERR＃信号也通过缓冲器置位，并提供给中断控制器的一个输入。 在替代实施例中，缓冲器使能输入连接到第一SERR＃信号和连接到第二SERR＃信号的缓冲器输出。 该装置还接收第一和第二PERR＃信号，并且将信号逻辑或运算在一起以产生组合的PERR＃信号。 将组合的PERR＃信号提供给由PCI系统时钟计时的寄存器，以在将PERR＃信号提供给中断控制器的第二个输入之前将组合的PERR＃信号同步到PCI时钟。 中断控制器向处理器产生中断，并使处理器轮询设备以识别可能导致错误的电路板并采取纠正措施。
-
公开(公告)号：US5590316A
公开(公告)日：1996-12-31
申请号：US445184
申请日：1995-05-19
申请人： Brian S. Hausauer
发明人： Brian S. Hausauer
CPC分类号： G06F1/08
摘要： An apparatus is disclosed for smoothly multiplying the frequency of a computer's basic clock during a burst transfer cycle and smoothly resuming the basic clock frequency upon completing the burst transfer cycle. A fixed frequency multiplier is connected to the basic clock to generate a clock whose frequency is a multiple of the basic clock frequency. A decoder which operates synchronously with the fixed frequency multiplier clock responds to control signals of the expansion bus to detect the start and the end of a burst transfer cycle. The decoder also toggles a speed-up signal during the burst transfer cycle on the rising edges of the fixed frequency multiplier clock. The speed-up signal and the basic clock is provided to a variable frequency multiplier which multiplies the frequency of the basic clock when the speed-up signal is toggled and reproduces the frequency of the basic clock when the speed-up signal is deasserted, thus providing a clock signal whose rising edges are aligned with the rising and falling edges of the basic clock and whose frequency is a multiple of the basic clock frequency during the burst transfer cycle.
摘要翻译： 公开了一种用于在突发传送周期期间平滑地乘以计算机基本时钟的频率并且在完成突发传送周期时平滑地恢复基本时钟频率的装置。 固定倍频器连接到基本时钟以产生频率是基本时钟频率的倍数的时钟。 与固定倍频器时钟同步工作的解码器响应于扩展总线的控制信号，以检测突发传送周期的开始和结束。 解码器还在固定倍频器时钟的上升沿期间在突发传送周期期间切换加速信号。 加速信号和基本时钟被提供给可变倍频器，当加速信号被切换时，可变倍频器乘以基本时钟的频率，并且当加速信号被无效时再现基本时钟的频率，因此 提供时钟信号，其上升沿与基本时钟的上升沿和下降沿对齐，并且其频率是脉冲串传送周期期间的基本时钟频率的倍数。
-
23.再颁专利公开(公告)号：USRE37980E1
公开(公告)日：2003-02-04
申请号：US09706883
申请日：2000-11-03
IPC分类号： G06F1300
CPC分类号： G06F13/4027 , G06F13/4059
摘要： A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches a bridge interface from the PCI bus, and it is recognized that the address is within the fast burst range, then the fast burst mode is allowed, and write or read requests can be issued without waiting for the snoop phase, since there is no possibility of defer or retry.
摘要翻译： 计算机系统在微处理器本身的控制下具有处理器总线，并且该总线与主存储器通信，为大多数缓存填充操作提供高性能访问。 此外，该系统包括一个或多个扩展总线，优选地在示例性实施例中为PCI类型。 主机到PCI桥接器用于将处理器总线耦合到扩展总线。 例如，其他总线可以通过PCI至（E）ISA网桥耦合到PCI总线。 主机到PCI桥接器包含发布的写入和延迟读取请求的队列。 所有交易排队通过桥梁，上游或下游。 系统总线是超级管道，因为交易重叠。 在桥接器和主存储器之间允许快速突发事务，即，可以在不延迟或重试的情况下满足的请求被应用于系统总线，而不等待从目标获得响应。 地址范围（例如，系统存储器地址）被定义为快速突发范围，并且该范围内的任何地址与该范围之外的地址不同。 通过配置周期对桥进行编程，以建立此快速突发范围，在此范围内，已知无法接收到无序响应。 当事务从PCI总线到达桥接口时，并且认识到地址在快速突发范围内，则允许快速突发模式，并且可以发出写入或读取请求而不等待窥探阶段，因为 没有推迟或重试的可能性。
-
24.发明授权Host bridge configured to mask a portion of peripheral devices coupled to a bus further downstream of the host bridge from a host processor 失效主桥被配置为掩蔽耦合到主主机的主机桥下游的总线的外围设备的一部分与主机处理器
公开(公告)号：US6141708A
公开(公告)日：2000-10-31
申请号：US98015
申请日：1998-06-15
CPC分类号： G06F13/4027
摘要： A computer system with an Intelligent Input/Output architecture having a scheme for hiding at least a portion of peripheral devices. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, a first input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices operably connected to the I/O bus for transferring data in I/O transactions. A masking module is provided for rendering at least a portion of the plurality of peripheral devices hidden from the host operating system and host processors. The masking module is configured upon system initialization and the contents of the module are used in blocking IDSEL signals associated with the portion of peripheral devices subordinated to an I/O processor.
摘要翻译： 具有智能输入/输出架构的计算机系统具有用于隐藏至少一部分外围设备的方案。 该计算机系统包括至少一个用于执行主机操作系统的主机处理器，主机处理器设置在主机总线上，第一输入/输出（I / O）总线，可操作地经主机到总线桥接到主机总线 以及可操作地连接到I / O总线以在I / O事务中传送数据的多个外围设备。 提供掩蔽模块，用于使从主机操作系统和主处理器隐藏的多个外围设备的至少一部分。 掩蔽模块在系统初始化时配置，并且模块的内容用于阻止与从属于I / O处理器的外围设备的部分相关联的IDSEL信号。
-
25.发明授权Delivering a request to write or read data before delivering an earlier write request 失效在提交较早的写入请求之前提交写入或读取数据的请求
公开(公告)号：US6138192A
公开(公告)日：2000-10-24
申请号：US777575
申请日：1996-12-31
申请人： Brian S. Hausauer
发明人： Brian S. Hausauer
CPC分类号： G06F13/4059
摘要： A bridge device for delivering data transactions between devices on two data buses in a computer system includes, for each pair of devices that may transact across the bridge device, a dedicated storage area that aids in completing transactions between the devices in the pair. The bridge device also includes a controller that allows transactions in one dedicated storage area to be completed without regard to the completion of earlier-issued transactions in another dedicated storage area.
摘要翻译： 用于在计算机系统中的两个数据总线上的设备之间递送数据事务的桥接设备包括用于跨越桥接设备交互的每对设备，辅助完成该对中的设备之间的事务的专用存储区域。 桥接设备还包括控制器，其允许在一个专用存储区域中的事务完成，而不考虑在另一专用存储区域中完成先前发布的事务。
-
公开(公告)号：US06438627B1
公开(公告)日：2002-08-20
申请号：US09076561
申请日：1998-05-12
IPC分类号： G06F1314
CPC分类号： G06F13/28 , G06F12/0215
摘要： An apparatus is disclosed for predicting and making available in advance certain information, namely the address signals from an expansion bus, so as to relax the timing requirement of the burst transfer cycle. A decoder responds to the control signals of the expansion bus to detect the start and the end of a burst transfer cycle. The decoder controls a counter, which stores the initial address signals of the expansion bus at the start of the burst transfer cycle and predicts the initial address signals by incrementing the address signals during the burst transfer cycle. A multiplexer couples either the predicted address signal to the multiplexer output during the burst transfer cycle or the address signal of the EISA bus to the multiplexer output when the computer system is not performing the EMB burst transfer cycle. In another aspect of the present invention, the low order address signal of the bus is predicted using a second counter. The output of the second counter is merged into the low order address signal of the bus interface devices to properly index the second word of the burst transfer cycle.
摘要翻译： 公开了一种用于预测并提供某些信息（即来自扩展总线的地址信号）以便放松突发传送周期的定时要求的装置。 解码器响应扩展总线的控制信号以检测突发传送周期的开始和结束。 解码器控制计数器，该计数器在突发传送周期开始时存储扩展总线的初始地址信号，并通过在突发传送周期期间递增地址信号来预测初始地址信号。 当计算机系统不执行EMB突发传输周期时，多路复用器将突发传送周期期间的预测地址信号与EISA总线的地址信号耦合到多路复用器输出。 在本发明的另一方面，使用第二计数器预测总线的低阶地址信号。 第二计数器的输出被合并到总线接口设备的低位地址信号中，以适当地对突发传送周期的第二个字进行索引。
-
公开(公告)号：US5870567A
公开(公告)日：1999-02-09
申请号：US775300
申请日：1996-12-31
CPC分类号： G06F13/4027
摘要： A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available. A contemporary microprocessor such as a P6 has a deferred transaction protocol to implement split transactions, but this protocol is not available on a PCI bus. Split transactions are done by a "retry" command on a PCI bus, wherein a read request that cannot be completed immediately is queued and a "retry" response is sent back to the requester on the bus; this instructs the requester to retry (send the same command again) at a later time.
摘要翻译： 计算机系统在微处理器本身的控制下具有处理器总线，并且该总线与主存储器通信，为大多数缓存填充操作提供高性能访问。 此外，该系统包括一个或多个扩展总线，优选地在示例性实施例中为PCI类型。 主机到PCI桥接器用于将处理器总线耦合到扩展总线。 例如，其他总线可以通过PCI至（E）ISA网桥耦合到PCI总线。 主机到PCI桥接器包含发布的写入和延迟读取请求的队列。 所有交易排队通过桥梁，上游或下游。 根据本发明的特征，提供分割事务，即，在请求它的处理器仍然在总线上时不满足的读请求，而是在读取结果为止之前放弃总线并且其他事务干预 可用。 诸如P6的当代微处理器具有延迟事务协议来实现分离事务，但是该协议在PCI总线上不可用。 拆分事务通过PCI总线上的“重试”命令完成，其中立即不能完成的读取请求被排队，并且“重试”响应被发送回总线上的请求者; 这指示请求者稍后重试（再次发送相同的命令）。
-
公开(公告)号：US5835741A
公开(公告)日：1998-11-10
申请号：US777597
申请日：1996-12-31
CPC分类号： G06F13/4027 , G06F13/4059
摘要： A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches a bridge interface from the PCI bus, and it is recognized that the address is within the fast burst range, then the fast burst mode is allowed, and write or read requests can be issued without waiting for the snoop phase, since there is no possibility of defer or retry.
-
29.发明授权Stopclock toggle system for powering two CPUs from a regulator only sized for one CPU 失效停止时钟切换系统，用于为仅适用于一个CPU的稳压器供电两个CPU
公开(公告)号：US5659789A
公开(公告)日：1997-08-19
申请号：US573963
申请日：1995-12-15
CPC分类号： G06F1/26 , G06F11/2015
摘要： The present invention relates to a fault tolerant system for providing power to a multiple central processing unit computer system. Three DC-DC converters, each sized for providing power to one central processing unit, furnish power to two central processing units through two power planes. Each DC-DC converter has an output voltage level selectable through a voltage identification signal. If the voltage identification signals of the converters match, identification logic couples the power planes together. If only one converter is available to power the two central processing units, a stopclock logic circuit alternatively places the central processing units in known stopclock modes. Thus, the single converter only has to fully power one central processing unit at any one time.
摘要翻译： 本发明涉及一种用于向多个中央处理单元计算机系统提供电力的容错系统。 三个DC-DC转换器，每个尺寸适于向一个中央处理单元提供电源，通过两个电源平面向两个中央处理单元提供电力。 每个DC-DC转换器具有可通过电压识别信号选择的输出电压电平。 如果转换器的电压识别信号匹配，识别逻辑将电源层耦合在一起。 如果只有一个转换器可用于为两个中央处理单元供电，则停止时钟逻辑电路交替地将中央处理单元置于已知的停止时钟模式。 因此，单个转换器只需要在任何一个时间完全为一个中央处理器供电。
-
-
-
-
-
-
-
-
搜索结果
29 条记录 (耗时 0.029 秒)
