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    Audio clock regenerator with precise parameter transformer
    22.
    发明申请
    Audio clock regenerator with precise parameter transformer 有权
    具有精密参数变压器的音频时钟再生器

    公开(公告)号：US20090167366A1

    公开(公告)日：2009-07-02

    申请号：US11965261

    申请日：2007-12-27

    Applicant: Hui-Min Wang

    Inventor： Hui-Min Wang

    IPC: H03B21/00 ,  H03B19/00

    CPC classification number: H04N5/775 ,  G09G2370/04 ,  G09G2370/12 ,  H04N5/7755 ,  H04N21/242 ,  H04N21/4302

    Abstract: It is difficult to implement a conventional phase lock loop circuit in a sink device within an HDMI system because the low frequency input causes the conventional phase lock loop circuit to absorb unnecessary noise during a long waiting period. Therefore, the present invention provides a low jitter clock regenerator comprises: an input clock; a divider to divide said input clock into a slower clock; a phase lock loop circuit to regenerate said slower clock to a reference clock; and a parameter transformer to tune said divider and said phase lock loop circuit to increase the adjustment speed of said phase lock loop circuit. The present invention also provides a method to reorganize parameters in order to create new parameters which are better suitable for a clock recovery circuit in a sink device within an HDMI system.

    Abstract translation: 由于低频输入导致常规锁相环电路在长时间等待期间吸收不必要的噪声，所以难以在HDMI系统内的宿设备中实现传统的锁相环电路。 因此，本发明提供了一种低抖动时钟再生器，包括：输入时钟; 分频器，用于将所述输入时钟分频成较慢的时钟; 用于将所述较慢时钟再生成参考时钟的锁相环电路; 以及参数变压器，用于调谐所述分频器和所述锁相环电路，以增加所述锁相环电路的调节速度。 本发明还提供了一种重组参数以便创建更适合于HDMI系统内的接收器装置中的时钟恢复电路的新参数的方法。

    Digital-to-analog converter
    23.
    发明授权
    Digital-to-analog converter 失效
    数模转换器

    公开(公告)号：US07474245B1

    公开(公告)日：2009-01-06

    申请号：US11898538

    申请日：2007-09-13

    Applicant: Hui-Min Wang ,  Chen-Song Yen ,  Chin-Tien Chang ,  Chuan-Che Lee

    Inventor： Hui-Min Wang ,  Chen-Song Yen ,  Chin-Tien Chang ,  Chuan-Che Lee

    IPC: H03M1/68

    CPC classification number: H03M1/682 ,  H03M1/765

    Abstract: A digital-to-analog converter outputting an output analog voltage according to an N-bit digital signal is provided. The digital-to-analog converter includes a first and a second resistor strings, a first and a second select units. The first resistor string is connected between a first and a second power supply voltages to generate a first group of reference voltages. The first select unit selects two reference voltages out of the first group according to M most significant bits of the N-bit digital signal. The second resistor string is connected between the selected reference voltages to generate a second group of reference voltages between the selected reference voltages. The second select unit selects one reference voltage out of the second group as the output analog voltage according to the N-M least significant bits of the N-bit digital signal.

    Abstract translation: 提供了根据N位数字信号输出输出模拟电压的数模转换器。 数模转换器包括第一和第二电阻串，第一和第二选择单元。 第一电阻串连接在第一和第二电源电压之间以产生第一组参考电压。 第一选择单元根据N位数字信号的M个最高有效位选择第一组中的两个参考电压。 第二电阻串连接在所选择的参考电压之间，以在所选参考电压之间产生第二组参考电压。 第二选择单元根据N位数字信号的N-M个最低有效位选择第二组中的一个参考电压作为输出模拟电压。

    CURRENT MODE INTERFACE RECEIVER WITH PROCESS INSENSITIVE COMMON MODE CURRENT EXTRACTION AND THE METHOD
    24.
    发明申请
    CURRENT MODE INTERFACE RECEIVER WITH PROCESS INSENSITIVE COMMON MODE CURRENT EXTRACTION AND THE METHOD 有权
    电流模式界面接收器，具有无源共模电流提取和方法

    公开(公告)号：US20080165898A1

    公开(公告)日：2008-07-10

    申请号：US11621918

    申请日：2007-01-10

    Applicant: Hui-Min Wang

    Inventor： Hui-Min Wang

    IPC: H04L25/06

    CPC classification number: H04L25/0294 ,  H04L25/0282

    Abstract: A data communication system comprises a transmitter and a receiver. A plurality of current mode drivers at the transmitter are used to transmit clock and data signals to the receiver. A plurality of current mode sinks at the receiver are used to receive the transmitted clock and data signal. The present invention provides an improved current mode interface receiver with a process insensitive common mode current extraction circuit. The proposed common mode current extraction circuit will generate a current reference based on the received clock signal, so as to accurately interpret the received clock and data signals.

    Abstract translation: 数据通信系统包括发射机和接收机。 发射机处的多个电流模式驱动器用于将时钟和数据信号传输到接收机。 在接收机处的多个当前模式信宿用于接收传输的时钟和数据信号。 本发明提供一种具有过程不敏感共模电流提取电路的改进的电流模式接口接收器。 所提出的共模电流提取电路将基于所接收的时钟信号产生电流参考，以便准确地解释所接收的时钟和数据信号。

    Pixel driving method of organic light emitting diode display and apparatus thereof
    25.
    发明申请
    Pixel driving method of organic light emitting diode display and apparatus thereof 审中-公开
    有机发光二极管显示器的像素驱动方法及其装置

    公开(公告)号：US20070222719A1

    公开(公告)日：2007-09-27

    申请号：US11436226

    申请日：2006-05-17

    Applicant: Hui-Min Wang ,  Yu-Wen Chiou

    Inventor： Hui-Min Wang ,  Yu-Wen Chiou

    IPC: G09G3/32

    CPC classification number: G09G3/3233 ,  G09G3/3291 ,  G09G2310/0251 ,  G09G2310/061 ,  G09G2320/0233

    Abstract: A method pixel driving method of an organic light emitting diode (OLED) display and an apparatus thereof are provided. The method comprises the following steps. First, a pixel unit is reset to a predetermined voltage in a reset time period. After that, a frame period is divided into two driving time periods so that the pixel unit is finally charged to a pixel voltage. The charging process of the pixel unit is that the pixel unit is charged to a ground level in a first driving time period, and then the pixel unit is charged to the pixel voltage in a second driving time period.

    Abstract translation: 提供了一种有机发光二极管（OLED）显示器的方法像素驱动方法及其装置。 该方法包括以下步骤。 首先，在复位时间段内将像素单元复位到预定的电压。 之后，将帧周期分为两个驱动时间段，使得像素单元最终被充电到像素电压。 像素单元的充电处理是在第一驱动时间段内将像素单元充电到地电平，然后在第二驱动时间段内将像素单元充电到像素电压。

    Collapsible container
    26.
    发明授权
    Collapsible container 失效
    可折叠集装箱

    公开(公告)号：US07014057B2

    公开(公告)日：2006-03-21

    申请号：US10671053

    申请日：2003-09-22

    Applicant: Hui-Min Wang

    Inventor： Hui-Min Wang

    IPC: B65D6/16

    CPC classification number: B65D5/3614 ,  B65D2313/02

    Abstract: A collapsible container includes a rectangular bottom, a front and a rear rectangular wall pivotally turnably connected to a front and a rear edge, respectively, of the bottom along two folding lines, two rectangular side walls pivotally turnably connected to two lateral ends of each of the front and the rear wall along two folding lines, and two locating flaps pivotally turnably connected to two lateral edges of the bottom along two folding lines. Each of the two locating flaps is an isosceles triangle having two equal lateral sides separately corresponding to a diagonal of the side wall. Moreover, fastening elements are correspondingly provided on an inner surface of each side wall and an outer surface of the locating flap to enable detachable connection of the side walls to the locating flaps and accordingly free collapse and extension of the container.

    Abstract translation: 可折叠容器包括矩形底部，前后矩形壁，其分别沿着两条折叠线可转动地连接到底部的前边缘和后边缘，两个矩形侧壁可转动地连接到每个的两个侧端 沿着两条折叠线的前壁和后壁，以及沿两条折叠线可枢转地可转动地连接到底部的两个侧边缘的两个定位翼片。 两个定位翼片中的​​每一个是具有分别对应于侧壁的对角线的两个相等侧边的等腰三角形。 此外，紧固元件相应地设置在每个侧壁的内表面和定位翼片的外表面上，以使得侧壁能够与定位翼片可拆卸地连接，并因此自由地使容器的塌缩和延伸。

    VOLTAGE REGULATOR, AND INTEGRATED CIRCUIT USING THE SAME
    29.
    发明申请
    VOLTAGE REGULATOR, AND INTEGRATED CIRCUIT USING THE SAME 审中-公开
    电压调节器和使用该电压调节器的集成电路

    公开(公告)号：US20110095737A1

    公开(公告)日：2011-04-28

    申请号：US12606468

    申请日：2009-10-27

    Applicant: Yuan-Kai Chu ,  Hui-Min Wang

    Inventor： Yuan-Kai Chu ,  Hui-Min Wang

    IPC: G05F1/10

    CPC classification number: G05F1/575

    Abstract: A voltage regulator and an integrated circuit using the voltage regulator is provided. The voltage regulator has a bandgap reference circuit, an operational amplifier, a power transistor and a voltage divider. The bandgap reference circuit generates a bandgap reference voltage. The operational amplifier receives the bandgap reference voltage and a feedback voltage to output a control signal for the power transistor. The power transistor is powered by a first voltage source and transforms the first voltage source to a second voltage source according to the control signal. The second voltage source is divided by the voltage divider to generate the feedback voltage and is further used in powering the bandgap reference circuit and the operational amplifier.

    Abstract translation: 提供了使用电压调节器的电压调节器和集成电路。 电压调节器具有带隙参考电路，运算放大器，功率晶体管和分压器。 带隙参考电路产生带隙参考电压。 运算放大器接收带隙参考电压和反馈电压以输出功率晶体管的控制信号。 功率晶体管由第一电压源供电，并根据控制信号将第一电压源转换为第二电压源。 第二电压源由分压器分压以产生反馈电压，并进一步用于为带隙基准电路和运算放大器供电。

    Liquid Crystal Display and Source Driving Circuit Thereof
    30.
    发明申请
    Liquid Crystal Display and Source Driving Circuit Thereof 有权
    液晶显示器和源极驱动电路

    公开(公告)号：US20100134470A1

    公开(公告)日：2010-06-03

    申请号：US12327376

    申请日：2008-12-03

    Applicant: Lin-Kai Bu ,  Hui-Min Wang

    Inventor： Lin-Kai Bu ,  Hui-Min Wang

    IPC: G06F3/038 ,  G09G3/28

    CPC classification number: G09G3/3688 ,  G09G3/3696 ,  G09G2320/0276

    Abstract: A source driving circuit includes a gamma voltage generator, a common voltage generator and a driver. The gamma voltage generator receives gamma data from a timing controller through reduced swing differential signaling (RSDS) transmission interface to generate corresponding gamma voltages. The common voltage generator receives common voltage data from the timing controller to generate a corresponding common voltage. The driver receives image data from the timing controller through the RSDS transmission interface, the gamma voltages from the gamma voltage generator and the common voltage from the common voltage generator for modifying the image data using the gamma voltages and the common voltage and transmitting the modified image data to a panel of the liquid crystal display.

    Abstract translation: 源极驱动电路包括伽马电压发生器，公共电压发生器和驱动器。 伽马电压发生器通过减小的摆幅差分信号（RSDS）传输接口从定时控制器接收伽马数据，以产生相应的伽马电压。 公共电压发生器从定时控制器接收公共电压数据以产生相应的公共电压。 驱动器通过RSDS传输接口从定时控制器接收图像数据，伽马电压发生器的伽马电压和来自公共电压发生器的公共电压，以使用伽马电压和公共电压修改图像数据，并发送修改的图像 数据到液晶显示器的面板。

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