VOLTAGE REGULATOR, AND INTEGRATED CIRCUIT USING THE SAME
    1.
    发明申请
    VOLTAGE REGULATOR, AND INTEGRATED CIRCUIT USING THE SAME 审中-公开
    电压调节器和使用该电压调节器的集成电路

    公开(公告)号:US20110095737A1

    公开(公告)日:2011-04-28

    申请号:US12606468

    申请日:2009-10-27

    IPC分类号: G05F1/10

    CPC分类号: G05F1/575

    摘要: A voltage regulator and an integrated circuit using the voltage regulator is provided. The voltage regulator has a bandgap reference circuit, an operational amplifier, a power transistor and a voltage divider. The bandgap reference circuit generates a bandgap reference voltage. The operational amplifier receives the bandgap reference voltage and a feedback voltage to output a control signal for the power transistor. The power transistor is powered by a first voltage source and transforms the first voltage source to a second voltage source according to the control signal. The second voltage source is divided by the voltage divider to generate the feedback voltage and is further used in powering the bandgap reference circuit and the operational amplifier.

    摘要翻译: 提供了使用电压调节器的电压调节器和集成电路。 电压调节器具有带隙参考电路,运算放大器,功率晶体管和分压器。 带隙参考电路产生带隙参考电压。 运算放大器接收带隙参考电压和反馈电压以输出功率晶体管的控制信号。 功率晶体管由第一电压源供电,并根据控制信号将第一电压源转换为第二电压源。 第二电压源由分压器分压以产生反馈电压,并进一步用于为带隙基准电路和运算放大器供电。

    Liquid crystal display and source driving circuit having a gamma and common voltage generator thereof
    2.
    发明授权
    Liquid crystal display and source driving circuit having a gamma and common voltage generator thereof 有权
    具有伽马和公共电压发生器的液晶显示器和源极驱动电路

    公开(公告)号:US08184078B2

    公开(公告)日:2012-05-22

    申请号:US12327376

    申请日:2008-12-03

    IPC分类号: G09G3/36

    摘要: A source driving circuit includes a gamma voltage generator, a common voltage generator and a driver. The gamma voltage generator receives gamma data from a timing controller through reduced swing differential signaling (RSDS) transmission interface to generate corresponding gamma voltages. The common voltage generator receives common voltage data from the timing controller to generate a corresponding common voltage. The driver receives image data from the timing controller through the RSDS transmission interface, the gamma voltages from the gamma voltage generator and the common voltage from the common voltage generator for modifying the image data using the gamma voltages and the common voltage and transmitting the modified image data to a panel of the liquid crystal display.

    摘要翻译: 源极驱动电路包括伽马电压发生器,公共电压发生器和驱动器。 伽马电压发生器通过减小的摆幅差分信号(RSDS)传输接口从定时控制器接收伽马数据,以产生相应的伽马电压。 公共电压发生器从定时控制器接收公共电压数据以产生相应的公共电压。 驱动器通过RSDS传输接口从定时控制器接收图像数据,伽马电压发生器的伽马电压和来自公共电压发生器的公共电压,以使用伽马电压和公共电压修改图像数据,并发送修改的图像 数据到液晶显示器的面板。

    Method and apparatus for adjusting serial data signal
    3.
    发明授权
    Method and apparatus for adjusting serial data signal 有权
    调整串行数据信号的方法和装置

    公开(公告)号:US07991097B2

    公开(公告)日:2011-08-02

    申请号:US11905797

    申请日:2007-10-04

    申请人: Hui-Min Wang

    发明人: Hui-Min Wang

    IPC分类号: H04L7/00

    摘要: A method for adjusting a serial data signal having multiple sets of bits includes the following steps. First, one set of bits in the serial data signal is over-sampled to generate a first set of over-sampled bits. Next, every adjacent two bits of the first set of over-sampled bits are compared to generate one set of edge bits. Then, a delay operation is determined according to the set of edge bits. Afterwards, a displacement operation is executed on next sets of bits in the serial data signal according to the delay operation.

    摘要翻译: 一种用于调整具有多组位数的串行数据信号的方法包括以下步骤。 首先,串行数据信号中的一组位被过采样以产生第一组过采样位。 接下来,比较第一组过采样比特的每个相邻的两比特以产生一组边缘比特。 然后,根据边缘位的集合来确定延迟操作。 然后,根据延迟动作对串行数据信号中的下一组位执行位移动作。

    Audio clock regenerator with precise parameter transformer

    公开(公告)号:US08441575B2

    公开(公告)日:2013-05-14

    申请号:US11965261

    申请日:2007-12-27

    申请人: Hui-Min Wang

    发明人: Hui-Min Wang

    摘要: It is difficult to implement a conventional phase lock loop circuit in a sink device within an HDMI system because the low frequency input causes the conventional phase lock loop circuit to absorb unnecessary noise during a long waiting period. Therefore, the present invention provides a low jitter clock regenerator comprises: an input clock; a divider to divide said input clock into a slower clock; a phase lock loop circuit to regenerate said slower clock to a reference clock; and a parameter transformer to tune said divider and said phase lock loop circuit to increase the adjustment speed of said phase lock loop circuit. The present invention also provides a method to reorganize parameters in order to create new parameters which are better suitable for a clock recovery circuit in a sink device within an HDMI system.

    Data transmission system and method thereof
    8.
    发明授权
    Data transmission system and method thereof 有权
    数据传输系统及其方法

    公开(公告)号:US07885362B2

    公开(公告)日:2011-02-08

    申请号:US11907859

    申请日:2007-10-18

    申请人: Hui-Min Wang

    发明人: Hui-Min Wang

    IPC分类号: H04L27/00

    摘要: A data transmission system includes a transmitter and a receiver. The transmitter mixes an original clock signal and an original data signal to generate and output a hybrid differential signal, the hybrid differential signal having multiple clock pulses and multiple data pulses. At lease one data pulse occurs between two clock pulses, and the period between two clock pulses corresponds to the frequency of the original clock signal. The clock pulses and the data pulses have different differential swings. The receiver receives the hybrid differential signal via a bus and generates a recovered clock signal and a recovered data signal based on the hybrid differential signal. The hybrid differential signal, the original clock signal and the original data signal are reduced swing differential signals.

    摘要翻译: 数据传输系统包括发射机和接收机。 发射机混合原始时钟信号和原始数据信号,以产生和输出混合差分信号,混合差分信号具有多个时钟脉冲和多个数据脉冲。 在两个时钟脉冲之间至少发生一个数据脉冲,两个时钟脉冲之间的周期对应于原始时钟信号的频率。 时钟脉冲和数据脉冲具有不同的差分摆幅。 接收机通过总线接收混合差分信号,并根据混合差分信号产生恢复的时钟信号和恢复的数据信号。 混合差分信号,原始时钟信号和原始数据信号是摆幅差分信号。

    Data transmission system and method thereof
    9.
    发明申请
    Data transmission system and method thereof 有权
    数据传输系统及其方法

    公开(公告)号:US20090103674A1

    公开(公告)日:2009-04-23

    申请号:US11907859

    申请日:2007-10-18

    申请人: Hui-Min Wang

    发明人: Hui-Min Wang

    IPC分类号: H03D3/24 G09G3/36 H04L7/00

    摘要: A data transmission system includes a transmitter and a receiver. The transmitter mixes an original clock signal and an original data signal to generate and output a hybrid differential signal, the hybrid differential signal having multiple clock pulses and multiple data pulses. At lease one data pulse occurs between two clock pulses, and the period between two clock pulses corresponds to the frequency of the original clock signal. The clock pulses and the data pulses have different differential swings. The receiver receives the hybrid differential signal via a bus and generates a recovered clock signal and a recovered data signal based on the hybrid differential signal. The hybrid differential signal, the original clock signal and the original data signal are reduced swing differential signals.

    摘要翻译: 数据传输系统包括发射机和接收机。 发射机混合原始时钟信号和原始数据信号以产生和输出混合差分信号,混合差分信号具有多个时钟脉冲和多个数据脉冲。 在两个时钟脉冲之间至少发生一个数据脉冲,两个时钟脉冲之间的周期对应于原始时钟信号的频率。 时钟脉冲和数据脉冲具有不同的差分摆幅。 接收机通过总线接收混合差分信号,并根据混合差分信号产生恢复的时钟信号和恢复的数据信号。 混合差分信号,原始时钟信号和原始数据信号是摆幅差分信号。

    Multi-channel receiver, digital edge tuning circuit and method thereof
    10.
    发明授权
    Multi-channel receiver, digital edge tuning circuit and method thereof 失效
    多通道接收机,数字边缘调谐电路及其方法

    公开(公告)号:US07450675B2

    公开(公告)日:2008-11-11

    申请号:US11160526

    申请日:2005-06-28

    IPC分类号: H04L7/00

    摘要: A multi-channel receiver, digital edge tuning circuit and a method for operating the same is disclosed. The digital edge tuning circuit for tuning phases of an input signal and a clock signal, comprises a delay-tuning circuit for receiving the input signal and delaying the input signal to generate a fine-tuned signal; a delay set comprising a plurality of delays connected serially one by one, the input of the delay set coupled to the fine-tune circuit, for receiving the fine-tuned signal; a plurality of sample/hold circuits, each of the sample/hold circuits coupled to a corresponding output of one of the delays and the fine-tune circuit, for sampling and holding the corresponding output; and a dynamic edge tuning circuit, coupled to the sample/hold circuits, for controlling a common delay time delayed by the delay-tuning circuit according to which one of the sample/hold circuits samples a data edge of the input signal.

    摘要翻译: 公开了一种多通道接收机,数字边缘调谐电路及其操作方法。 用于调谐输入信号和时钟信号的相位的数字边沿调谐电路包括延迟调谐电路,用于接收输入信号并延迟输入信号以产生微调信号; 延迟集合,包括串联地逐个连接的多个延迟,耦合到微调电路的延迟集合的输入,用于接收微调信号; 多个采样/保持电路,每个采样/保持电路耦合到延迟中的一个的对应输出和微调电路,用于采样和保持相应的输出; 以及耦合到采样/保持电路的动态边沿调谐电路,用于根据哪个采样/保持电路对输入信号的数据沿进行采样来控制由延迟调谐电路延迟的公共延迟时间。