公开(公告)号：US5960284A

公开(公告)日：1999-09-28

申请号：US985647

申请日：1997-12-05

申请人： Chrong Jung Lin ,  Shui-Hung Chen ,  Jong Chen ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Shui-Hung Chen ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11556 ,  H01L27/115

摘要： A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. Dope the sidewalls of the floating gate trench with a threshold implant through the trench sidewall surfaces. Form a tunnel oxide layer on the trench sidewall surfaces, the tunnel oxide layer having an outer surface. Form a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Form an interelectrode dielectric layer over the top surface of the floating gate electrode. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode. Form a source line by the step of performing a self-aligned etch followed by a source line implant.

摘要翻译： 通过以下步骤形成硅半导体衬底上的垂直存储器件。 在硅半导体衬底的表面上形成隔离氧化硅结构的阵列。 在硅半导体衬底中在阵列中的氧化硅结构之间形成浮栅沟槽，沟槽具有沟槽侧壁表面。 通过沟槽侧壁表面用阈值注入来掺杂浮栅沟槽的侧壁。 在沟槽侧壁表面上形成隧道氧化物层，隧道氧化物层具有外表面。 在隧道氧化物层的外表面上的沟槽中形成浮栅电极。 衬底中的源极/漏极区域与浮栅电极自对准。 在浮栅电极的顶表面上形成电极间电介质层。 在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极。 通过执行自对准蚀刻，然后进行源极线植入的步骤形成源极线。

公开(公告)号：US6127226A

公开(公告)日：2000-10-03

申请号：US995998

申请日：1997-12-22

申请人： Chrong-Jung Lin ,  Jong Chen ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chrong-Jung Lin ,  Jong Chen ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： This is a method of forming a vertical memory device on a semiconductor substrate. Start by forming an initial mask with a first array of parallel strips, with a first orientation, on the surface of a silicon oxide layer on a substrate. Then form another mask with transverse strips to form gate trench openings between the first array of strips and the transverse strips. Next, etch floating gate trenches in the substrate through the gate trench openings. Dope the walls of the trenches with a threshold implant and remove exposed portions of the mask. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Strip the remainder of the masks. Form a tunnel oxide layer on the trench surfaces and a floating gate electrode in the trench on the tunnel oxide layer. Above the source/drain regions, form source drain conductor lines in the substrate in a parallel array. Form an ONO dielectric layer and a control gate electrode over the top surface of the floating gate electrode and an array of P/N isolation regions in the silicon semiconductor substrate.

摘要翻译： 这是在半导体衬底上形成垂直存储器件的方法。 首先通过在衬底上的氧化硅层的表面上形成具有第一取向的平行条带的第一阵列的初始掩模。 然后形成具有横向条带的另一个掩模，以在第一阵列条和横向条之间形成栅极沟槽开口。 接下来，通过栅极沟槽开口在衬底中的蚀刻浮栅沟槽。 用阈值植入物掺杂沟槽的墙壁，并去除掩模的暴露部分。 衬底中的源极/漏极区域与浮栅电极自对准。 剥去其余的面具。 在沟槽表面上形成隧道氧化物层，并在隧道氧化物层上形成沟槽中的浮栅电极。 在源极/漏极区之上，以平行阵列形成衬底中的源极漏极导线。 在浮置栅电极的顶表面上形成ONO电介质层和控制栅电极以及硅半导体衬底中的P / N隔离区的阵列。

公开(公告)号：US6066874A

公开(公告)日：2000-05-23

申请号：US407108

申请日：1999-09-27

申请人： Chrong-Jung Lin ,  Shui-Hung Chen ,  Jong Chen ,  Di-Son Kuo

发明人： Chrong-Jung Lin ,  Shui-Hung Chen ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A vertical memory device on a silicon semiconductor substrate comprises a floating gate trench in the substrate. in the array, the trench. The walls of the floating gate trench were doped with a threshold implant through the trench surfaces. There is a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. There is a floating gate electrode in the trench on the outer surfaces of the tunnel oxide layer. There are source/drain regions in the substrate self-aligned with the floating gate electrode. The source line and a drain line form above the source region and the drain region respectively. An interelectrode dielectric layer overlies the top surface of the floating gate electrode, and the source line and the drain line, and there is a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode.

摘要翻译： 硅半导体衬底上的垂直存储器件包括衬底中的浮栅沟槽。 在阵列中，沟槽。 浮栅沟的壁通过沟槽表面掺杂有阈值注入。 在沟槽表面上存在隧道氧化物层，隧道氧化物层具有外表面。 在隧道氧化物层的外表面上的沟槽中存在浮栅电极。 衬底中的源极/漏极区域与浮置栅电极自对准。 源极线和漏极线分别形成在源极区域和漏极区域的上方。 电极间电介质层位于浮置栅电极的顶表面，源极线和漏极线之上，并且在浮栅电极的顶表面上方的电极间电介质层上方具有控制栅电极。

公开(公告)号：US6133097A

公开(公告)日：2000-10-17

申请号：US133969

申请日：1998-08-14

申请人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.

摘要翻译： 形成分离栅电极MOSFET器件的方法包括以下步骤。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成浮栅电极层。 在浮栅电极层上形成掩蔽帽。 掩模盖的图案中的隧道氧化物层和浮栅电极层形成的栅极电极堆叠。 栅电极中心的图案源极线槽向下堆叠到衬底。 在源线插槽的底部形成源区。 在覆盖堆叠的衬底上形成金属间电介质和控制栅极层。 将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。 形成自对准漏极区。

公开(公告)号：US6087222A

公开(公告)日：2000-07-11

申请号：US35058

申请日：1998-03-05

申请人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L21/336

CPC分类号： H01L27/11556 ,  H01L21/28273

摘要： A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.

公开(公告)号：US06391719B1

公开(公告)日：2002-05-21

申请号：US09575963

申请日：2000-05-23

申请人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11556 ,  H01L21/28273

摘要： A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.

摘要翻译： 形成垂直晶体管存储器件的方法包括以下步骤。 在形成沟槽之前，在行之间形成FOX区域。 在半导体衬底中形成具有侧壁和底部的一组沟槽，其中侧壁具有阈值注入区域。 在衬底的表面附近形成掺杂的漏极区域，并且在沟槽底部的器件的底部中的掺杂源极区域之间具有相反掺杂的沟道区域。 在包括沟槽的衬底上形成隧道氧化物层。 在隧道氧化物层上形成填充沟槽并在沟槽上方延伸的掺杂多晶硅的覆盖厚的浮栅层。 将浮动栅层蚀刻到沟槽顶部的下方。 在浮栅层和隧道氧化物层之上形成由ONO组成的电极间电介质层。 在电极间电介质层上形成掺杂多晶硅的厚度厚的控制栅极层。 将控制栅层图案化为控制栅电极。 形成与控制栅电极的侧壁相邻的间隔物。

公开(公告)号：US06583466B2

公开(公告)日：2003-06-24

申请号：US10117889

申请日：2002-04-08

申请人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L2976

CPC分类号： H01L27/11556 ,  H01L21/28273

摘要： A vertical transistor memory device includes FET cells formed in rows and columns with the rows orthogonally arranged relative to the columns. Several cells in a single row have a common source region and adjacent cells have a common drain region FOX regions are formed between the rows. A set of trenches are formed with sidewalls and a bottom in a semiconductor substrate with threshold implant regions formed in the sidewalls. Doped drain regions are formed near the surface of the substrate and doped source regions are formed in the base of the device below the trenches with oppositely doped channel regions therebetween. A tunnel oxide layer is formed over the substrate including the trenches aside from FOX regions. Floating gates of doped polysilicon are formed over the tunnel oxide layer in the trenches. An interelectrode dielectric layer covers the floating gate layer. Control gate electrodes of doped polysilicon are formed over the interelectrode dielectric layer. Spacers are formed adjacent to the sidewalls of the control gate electrode.

摘要翻译： 垂直晶体管存储器件包括以行和列形成的FET单元，其中相对于列正交布置的行。 单行中的几个单元具有共同的源极区域，并且相邻的单元具有共同的漏极区域，在行之间形成FOX区域。 在半导体衬底中形成具有在侧壁中形成的阈值注入区域的侧壁和底部的一组沟槽。 在衬底的表面附近形成掺杂的漏极区，并且掺杂源极区形成在沟槽下方的器件的底部，其间具有相反的掺杂沟道区。 在包括除FOX区域之外的沟槽的衬底上形成隧道氧化物层。 掺杂多晶硅的浮栅形成在沟槽中的隧道氧化物层上。 电极间电介质层覆盖浮栅层。 掺杂多晶硅的控制栅电极形成在电极间电介质层上。 间隔件邻近控制栅电极的侧壁形成。

公开(公告)号：US06326662B1

公开(公告)日：2001-12-04

申请号：US09633643

申请日：2000-08-07

申请人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.

摘要翻译： 形成分离栅电极MOSFET器件的方法包括以下步骤。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成浮栅电极层。 在浮栅电极层上形成掩蔽帽。 掩模盖的图案中的隧道氧化物层和浮栅电极层形成的栅极电极堆叠。 栅电极中心的图案源极线槽向下堆叠到衬底。 在源线插槽的底部形成源区。 在覆盖堆叠的衬底上形成金属间电介质和控制栅极层。 将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。 形成自对准漏极区。

公开(公告)号：US06538277B2

公开(公告)日：2003-03-25

申请号：US09920601

申请日：2001-08-02

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chuang-Ke Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin ,  Wen-Ting Chu

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chuang-Ke Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin ,  Wen-Ting Chu

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.

摘要翻译： 公开了一种形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多尖端）的新方法。 在不使用厚多晶硅层作为浮动栅极的情况下形成多尖端。 这可以通过在多晶硅上形成氧化层并氧化多晶硅的侧壁来实现。 由于浮栅的多晶硅的起始厚度相对较薄，所以形成的栅极尖或多尖端也必然是薄且尖锐的。 因此，该方法避免了超大规模集成技术的缩小设备中遇到的氧化物薄化问题，提高了EEPROM的快速可编程性和擦除性能。

公开(公告)号：US06534821B2

公开(公告)日：2003-03-18

申请号：US09927071

申请日：2001-08-10

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell. The vertical orientation of the source structure and the floating gate and the self-alignment of the spacer control gate to the floating gate together makes it possible to reduce the memory cell substantially.