公开(公告)号：US6011288A

公开(公告)日：2000-01-04

申请号：US995999

申请日：1997-12-22

申请人： Chrong-Jung Lin ,  Shui Hung Chen ,  Jong Chen ,  Di-Son Kuo

发明人： Chrong-Jung Lin ,  Shui Hung Chen ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A vertical memory device on a silicon semiconductor substrate comprises a floating gate trench in the substrate, in the array, the trench. The walls of the floating gate trench were doped with a threshold implant through the trench surfaces. There is a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. There is a floating gate electrode in the trench on the outer surfaces of the tunnel oxide layer. There are source/drain regions in the substrate self-aligned with the floating gate electrode. The source line and a drain line form above the source region and the drain region respectively. An interelectrode dielectric layer overlies the top surface of the floating gate electrode, and the source line and the drain line, and there is a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode.

摘要翻译： 硅半导体衬底上的垂直存储器件包括衬底中的浮置栅沟槽，阵列中的沟槽。 浮栅沟的壁通过沟槽表面掺杂有阈值注入。 在沟槽表面上存在隧道氧化物层，隧道氧化物层具有外表面。 在隧道氧化物层的外表面上的沟槽中存在浮栅电极。 衬底中的源极/漏极区域与浮置栅电极自对准。 源极线和漏极线分别形成在源极区域和漏极区域的上方。 电极间电介质层位于浮置栅电极的顶表面，源极线和漏极线之上，并且在浮栅电极顶表面上的电极间电介质层上方具有控制栅电极。

公开(公告)号：US6127226A

公开(公告)日：2000-10-03

申请号：US995998

申请日：1997-12-22

申请人： Chrong-Jung Lin ,  Jong Chen ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chrong-Jung Lin ,  Jong Chen ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： This is a method of forming a vertical memory device on a semiconductor substrate. Start by forming an initial mask with a first array of parallel strips, with a first orientation, on the surface of a silicon oxide layer on a substrate. Then form another mask with transverse strips to form gate trench openings between the first array of strips and the transverse strips. Next, etch floating gate trenches in the substrate through the gate trench openings. Dope the walls of the trenches with a threshold implant and remove exposed portions of the mask. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Strip the remainder of the masks. Form a tunnel oxide layer on the trench surfaces and a floating gate electrode in the trench on the tunnel oxide layer. Above the source/drain regions, form source drain conductor lines in the substrate in a parallel array. Form an ONO dielectric layer and a control gate electrode over the top surface of the floating gate electrode and an array of P/N isolation regions in the silicon semiconductor substrate.

摘要翻译： 这是在半导体衬底上形成垂直存储器件的方法。 首先通过在衬底上的氧化硅层的表面上形成具有第一取向的平行条带的第一阵列的初始掩模。 然后形成具有横向条带的另一个掩模，以在第一阵列条和横向条之间形成栅极沟槽开口。 接下来，通过栅极沟槽开口在衬底中的蚀刻浮栅沟槽。 用阈值植入物掺杂沟槽的墙壁，并去除掩模的暴露部分。 衬底中的源极/漏极区域与浮栅电极自对准。 剥去其余的面具。 在沟槽表面上形成隧道氧化物层，并在隧道氧化物层上形成沟槽中的浮栅电极。 在源极/漏极区之上，以平行阵列形成衬底中的源极漏极导线。 在浮置栅电极的顶表面上形成ONO电介质层和控制栅电极以及硅半导体衬底中的P / N隔离区的阵列。

公开(公告)号：US6066874A

公开(公告)日：2000-05-23

申请号：US407108

申请日：1999-09-27

申请人： Chrong-Jung Lin ,  Shui-Hung Chen ,  Jong Chen ,  Di-Son Kuo

发明人： Chrong-Jung Lin ,  Shui-Hung Chen ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A vertical memory device on a silicon semiconductor substrate comprises a floating gate trench in the substrate. in the array, the trench. The walls of the floating gate trench were doped with a threshold implant through the trench surfaces. There is a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. There is a floating gate electrode in the trench on the outer surfaces of the tunnel oxide layer. There are source/drain regions in the substrate self-aligned with the floating gate electrode. The source line and a drain line form above the source region and the drain region respectively. An interelectrode dielectric layer overlies the top surface of the floating gate electrode, and the source line and the drain line, and there is a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode.

摘要翻译： 硅半导体衬底上的垂直存储器件包括衬底中的浮栅沟槽。 在阵列中，沟槽。 浮栅沟的壁通过沟槽表面掺杂有阈值注入。 在沟槽表面上存在隧道氧化物层，隧道氧化物层具有外表面。 在隧道氧化物层的外表面上的沟槽中存在浮栅电极。 衬底中的源极/漏极区域与浮置栅电极自对准。 源极线和漏极线分别形成在源极区域和漏极区域的上方。 电极间电介质层位于浮置栅电极的顶表面，源极线和漏极线之上，并且在浮栅电极的顶表面上方的电极间电介质层上方具有控制栅电极。

公开(公告)号：US5970341A

公开(公告)日：1999-10-19

申请号：US988772

申请日：1997-12-11

申请人： Chrong-Jung Lin ,  Chia-Ta Hsieh ,  Jong Chen ,  Di-Son Kuo

发明人： Chrong-Jung Lin ,  Chia-Ta Hsieh ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

摘要： A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole. Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode and extending down into the control gate hole in the trench hole.

摘要翻译： 通过以下步骤提供在硅半导体衬底上形成垂直存储器分离栅极闪存器件的方法。 在硅半导体衬底中形成浮栅沟槽，沟槽具有沟槽表面。 在沟槽表面上形成隧道氧化物层，隧道氧化物层具有外表面。 形成填充隧道氧化物层的外表面上的沟槽的浮栅电极层。 衬底中的源极/漏极区域与浮栅电极层自对准。 通过从沟槽的漏极区域侧去除栅极电极层来对浮栅电极层进行构图。 在其中形成控制门孔。 在浮栅电极的顶表面上方，并在隧道氧化物层之上形成电极间电介质层。 在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极，并向下延伸到沟槽孔中的控制栅极孔。

公开(公告)号：US6133096A

公开(公告)日：2000-10-17

申请号：US208917

申请日：1998-12-10

申请人： Hung-Der Su ,  Jong Chen ,  Chrong-Jung Lin ,  Di-Son Kuo

发明人： Hung-Der Su ,  Jong Chen ,  Chrong-Jung Lin ,  Di-Son Kuo

IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11534

摘要： A process for integrating the fabrication of a flash memory cell, on a first region of a semiconductor substrate, with the fabrication of salicided peripheral devices, on a second region of the semiconductor substrate, has been developed. The flash memory cell features SAC contact structures, located between stacked gate structures, contacting underlying source/drain regions. The stack gate structures are comprised of a polycide control gate shape, on a dielectric layer, overlying a polysilicon floating gate shape. The performance of the peripheral devices are increased via use of metal silicide layers, located on the top surface of a polysilicon gate structure, as well as on the adjacent heavily doped source/drain regions.

摘要翻译： 已经开发了在半导体衬底的第二区域上将闪存单元的制造在半导体衬底的第一区域上与制造水银外围器件进行集成的工艺。 闪存单元具有位于层叠栅极结构之间的SAC接触结构，接触下层的源/漏区。 堆叠栅极结构由覆盖多晶硅浮栅形状的介电层上的多晶硅控制栅极形状构成。 通过使用位于多晶硅栅极结构的顶表面上的金属硅化物层以及相邻的重掺杂源极/漏极区域来增加外围器件的性能。

公开(公告)号：US6037223A

公开(公告)日：2000-03-14

申请号：US177342

申请日：1998-10-23

申请人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Di-Son Kuo

发明人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： A process for fabricating a flash memory cell, featuring self-aligned contact structures, overlying and contacting, self-aligned source, and self-aligned drain regions, located between stack gate structures, has been developed. The stack gate structures, located on an underlying silicon dioxide, tunnel oxide layer, are comprised of: a capping insulator shape; a polysilicon control gate shape; an inter-polysilicon dielectric shape; and a polysilicon floating gate shape. The use of self-aligned contact structures, and self-aligned source regions, allows increased cell densities to be achieved.

摘要翻译： 已经开发了一种用于制造闪存单元的方法，其特征在于位于堆叠栅极结构之间的自对准接触结构，覆盖和接触自对准源极和自对准漏极区。 位于下面的二氧化硅隧道氧化物层上的堆叠栅极结构包括：封盖绝缘体形状; 多晶硅控制门形状; 多晶硅间介质形状; 和多晶硅浮栅形状。 使用自对准接触结构和自对准的源区域可以实现提高的细胞密度。

公开(公告)号：US6001687A

公开(公告)日：1999-12-14

申请号：US283849

申请日：1999-04-01

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/8239

CPC分类号： H01L27/11521

摘要： When FLASH cells are made in association with STI (as opposed to LOCOS) it is often the case that stringers of silicon nitride are left behind after the spacers have been formed. This problem has been eliminated by requiring that the oxide in the STI trenches remain in place at the time that the silicon nitride spacers are formed. After that, the oxide is removed in the usual manner, following which a SALICIDE process is used to form a self aligned source line. When this sequence is followed no stringers are left behind on the walls of the trench, guaranteeing the absence of any open circuits or high resistance regions in the source line.

摘要翻译： 当与STI（与LOCOS相反）制成FLASH单元时，通常在形成间隔物之后留下氮化硅桁条。 通过要求在形成氮化硅间隔物的时刻STI槽中的氧化物保持在适当位置，已经消除了这个问题。 之后，以通常的方式去除氧化物，随后使用SALICIDE工艺来形成自对准的源极线。 当遵循该顺序时，沟槽的壁上不留下桁条，保证在源极线中不存在任何开路或高电阻区域。

公开(公告)号：US06251744B1

公开(公告)日：2001-06-26

申请号：US09356870

申请日：1999-07-19

申请人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Wen-Ting Chu ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Wen-Ting Chu ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L2176

CPC分类号： H01L21/76213

摘要： A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.

摘要翻译： 在半导体衬底的n阱或p阱区域上生长一层良好的氧化物。 在高电压器件区域中进行深n阱注入，随后是深n阱注入的深n阱驱动。 去除氧化物; 在高电压器件区域中产生场氧化物（FOX）区域。 牺牲氧化物层沉积在半导体衬底的表面上。 在半导体衬底的高电压PMOS区域中执行低电压簇n阱注入，随后是高压NMOS区，由低电压簇p阱注入，随后是埋置的p阱簇注入。

公开(公告)号：US06130168A

公开(公告)日：2000-10-10

申请号：US349844

申请日：1999-07-08

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

IPC分类号： H01L21/32 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/105 ,  H01L21/302

CPC分类号： H01L27/11526 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11546 ,  Y10S438/954

摘要： A new method of forming differential gate oxide thicknesses for both high and low voltage transistors is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas by shallow trench isolation regions. A polysilicon layer is deposited overlying a tunneling oxide layer on the surface of the substrate. The polysilicon and tunneling oxide layers are removed except in the memory cell area. An ONO layer is deposited overlying the polysilicon layer in the memory cell area and on the surface of the substrate in the low voltage and high voltage areas. The ONO layer is removed in the high voltage area. The substrate is oxidized in the high voltage area to form a thick gate oxide layer. Thereafter, the ONO layer is removed in the low voltage area and the substrate is oxidized to form a thin gate oxide layer. A second polysilicon layer is deposited over the ONO layer in the memory area, over the thin gate oxide layer in the low voltage area, and over the thick gate oxide layer in the high voltage area. The second polysilicon layer, ONO layer and first polysilicon layer in the memory cell area are patterned to form a control gate overlying a floating gate separated by the ONO layer. The second polysilicon layer is patterned to form a low voltage transistor in the low voltage area and a high voltage transistor in the high voltage area.

摘要翻译： 描述了为高压和低压晶体管形成差分栅极氧化物厚度的新方法。 提供半导体衬底，其中衬底的有源区域通过浅沟槽隔离区域与其它有源区域隔离。 沉积在衬底表面上的隧道氧化物层上的多晶硅层。 去除多晶硅和隧道氧化物层，除了在存储单元区域中。 沉积在存储单元区域中的多晶硅层和低电压和高电压区域的衬底表面上的ONO层。 在高电压区域中去除ONO层。 衬底在高压区域被氧化以形成厚的栅极氧化物层。 此后，在低电压区域中去除ONO层，并且衬底被氧化以形成薄的栅极氧化物层。 第二多晶硅层沉积在存储区域中的ONO层上，在低电压区域的薄栅极氧化物层上方，以及高电压区域中的厚栅极氧化物层上方。 将存储单元区域中的第二多晶硅层，ONO层和第一多晶硅层图案化以形成覆盖由ONO层分离的浮动栅极的控制栅极。 将第二多晶硅层图案化以在低电压区域中形成低压晶体管，并在高电压区域形成高压晶体管。

公开(公告)号：US6078076A

公开(公告)日：2000-06-20

申请号：US317645

申请日：1999-05-24

申请人： Chrong-Jung Lin ,  Chia-Ta Hsieh ,  Jong Chen ,  Di-Son Kuo

发明人： Chrong-Jung Lin ,  Chia-Ta Hsieh ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

摘要： A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode and extending down into the control gate hole in the trench hole.

摘要翻译： 通过以下步骤提供在硅半导体衬底上形成垂直存储器分离栅极闪存器件的方法。 在硅半导体衬底中形成浮栅沟槽，沟槽具有沟槽表面。 在沟槽表面上形成隧道氧化物层，隧道氧化物层具有外表面。 形成填充隧道氧化物层的外表面上的沟槽的浮栅电极层。 衬底中的源极/漏极区域与浮栅电极层自对准。 通过从沟槽的漏极区域侧去除栅极电极层来对浮栅电极层进行构图在其中形成控制栅极孔。 在浮栅电极的顶表面上方，并在隧道氧化物层之上形成电极间电介质层。 在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极，并向下延伸到沟槽孔中的控制栅极孔。