公开(公告)号：US6133097A

公开(公告)日：2000-10-17

申请号：US133969

申请日：1998-08-14

申请人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.

摘要翻译： 形成分离栅电极MOSFET器件的方法包括以下步骤。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成浮栅电极层。 在浮栅电极层上形成掩蔽帽。 掩模盖的图案中的隧道氧化物层和浮栅电极层形成的栅极电极堆叠。 栅电极中心的图案源极线槽向下堆叠到衬底。 在源线插槽的底部形成源区。 在覆盖堆叠的衬底上形成金属间电介质和控制栅极层。 将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。 形成自对准漏极区。

公开(公告)号：US06326662B1

公开(公告)日：2001-12-04

申请号：US09633643

申请日：2000-08-07

申请人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.

摘要翻译： 形成分离栅电极MOSFET器件的方法包括以下步骤。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成浮栅电极层。 在浮栅电极层上形成掩蔽帽。 掩模盖的图案中的隧道氧化物层和浮栅电极层形成的栅极电极堆叠。 栅电极中心的图案源极线槽向下堆叠到衬底。 在源线插槽的底部形成源区。 在覆盖堆叠的衬底上形成金属间电介质和控制栅极层。 将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。 形成自对准漏极区。

公开(公告)号：US06724036B1

公开(公告)日：2004-04-20

申请号：US09654776

申请日：2000-09-05

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： A stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling is described. An unconventionally high isolation oxide layer is formed in a shallow trench isolation (STI) in a substrate. The deep opening in the space between the STIs is conformally lined with a polysilicon to form a floating gate extending above the opening. A conformal intergate oxide lines the entire floating gate. A layer of polysilicon overlays the intergate oxide and protrudes downward into the openings to form a control gate with increased coupling to the floating gate.

摘要翻译： 描述了具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极闪存单元。 在衬底中的浅沟槽隔离（STI）中形成非常规的高隔离氧化层。 在STI之间的空间中的深开口共形地衬有多晶硅以形成在开口上方延伸的浮动栅极。 保形隔离层氧化物对整个浮动栅线进行排列。 一层多晶硅覆盖了间隔栅极氧化物并向下突出到开口中，以形成一个与浮动栅极增加耦合的控制栅极。

公开(公告)号：US06465836B2

公开(公告)日：2002-10-15

申请号：US09821199

申请日：2001-03-29

申请人： Chrong Jung Lin ,  Sheng-Wei Tsao ,  Di-Son Kuo ,  Jack Yeh ,  Wen-Ting Chu ,  Chung-Li Chang ,  Chia-Ta Hsieh

发明人： Chrong Jung Lin ,  Sheng-Wei Tsao ,  Di-Son Kuo ,  Jack Yeh ,  Wen-Ting Chu ,  Chung-Li Chang ,  Chia-Ta Hsieh

IPC分类号： H01L29788

CPC分类号： H01L29/7887 ,  H01L29/42336

摘要： Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field effect transistor (FET) device. Similarly, there is also formed within the split gate field effect transistor a floating gate electrode within the trench and covering within the trench a lower sub-portion of the channel region. Finally, the floating gate electrode in turn has formed vertically and horizontally overlapping thereover within the trench a control gate electrode which covers an upper sub-portion of the channel. The split gate field effect transistor (FET) device is fabricated with enhanced areal density and enhanced performance.

摘要翻译： 在分裂栅场效应晶体管（FET）器件和用于制造分离栅场效应晶体管（FET）器件的方法中，在半导体衬底内形成沟槽，其沟槽内的沟槽区域完全包含在分离栅极场内 效应晶体管（FET）器件。 类似地，在分裂栅极场效应晶体管内还形成有沟槽内的浮置栅电极，并且在沟槽内覆盖沟道区的下部子部分。 最后，浮栅电极依次形成在沟槽内垂直和水平重叠的覆盖通道的上部子部分的控制栅电极。 分离栅场效应晶体管（FET）器件制造具有增强的面密度和增强的性能。

公开(公告)号：US06297099B1

公开(公告)日：2001-10-02

申请号：US09765045

申请日：2001-01-19

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jack Yeh ,  Chrong Jung Lin ,  Wen-Ting Chu ,  Chung-Li Chang

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jack Yeh ,  Chrong Jung Lin ,  Wen-Ting Chu ,  Chung-Li Chang

IPC分类号： H01L218247

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  Y10S438/981

摘要： A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion. A polysilicon layer is formed over the interpoly oxide layer. The structure is patterned to form a floating gate/word line device.

摘要翻译： 一种制造浮栅/字线装置的方法，包括以下步骤。 提供半导体结构。 在半导体结构上方形成浮栅部分。 浮动门部分具有侧壁和顶面。 多晶氧化物部分形成在浮动栅极的顶表面上。 在半导体结构，多晶氧化物部分和多晶氧化物部分之上形成多层氧化物层。 所述多晶硅氧化物层具有初始厚度，并且包括：与所述浮动栅极部分相邻的所述半导体结构的至少一部分上的字线区域部分; 浮动部分侧壁上的侧壁区域部分; 以及多个氧化物部分上方的顶部。 互折层氧化物层的顶部的初始厚度减小到第二厚度，而不会减小多晶氧化物字线区域部分的初始厚度或多余氧化物侧壁区域部分的明显部分。 在多晶硅层上形成多晶硅层。 将结构图案化以形成浮动栅/字线装置。

公开(公告)号：US6153494A

公开(公告)日：2000-11-28

申请号：US310257

申请日：1999-05-12

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

IPC分类号： H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： A method is provided for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. This is accomplished by first depositing an unconventionally high or thick layer of nitride and then forming a shallow trench isolation (STI) through the nitride layer into the substrate, filling the STI with isolation oxide, removing the nitride thus leaving behind a deep opening about the filled STI, filling conformally the opening with a first polysilicon layer to form a floating gate, forming interpoly oxide layer over the floating gate, and then forming a second polysilicon layer to form the control gate and finally forming the self-aligned source of the stacked-gate flash memory cell of the invention. A stacked-gate flash memory cell is also provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.

摘要翻译： 提供一种用于形成具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极快闪存储器单元的方法。 这是通过首先沉积非常规高或较厚的氮化物层，然后通过氮化物层形成浅沟槽隔离（STI）到衬底中，用隔离氧化物填充STI，从而除去氮化物，从而留下围绕 填充STI，用第一多晶硅层保形地填充开口以形成浮置栅极，在浮置栅极上形成多晶硅层，然后形成第二多晶硅层以形成控制栅极，并最终形成堆叠的自对准源 本发明的闪存单元。 还提供了堆叠栅极闪存单元，其具有具有高阶氧化物和高横向耦合的浅沟槽隔离。

公开(公告)号：US06437397B1

公开(公告)日：2002-08-20

申请号：US09377539

申请日：1999-08-19

申请人： Chrong Jung Lin ,  Shui-Hung Chen ,  Jong Chen ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Shui-Hung Chen ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11556 ,  H01L27/115

摘要： A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. Dope the sidewalls of the floating gate trench with a threshold implant through the trench sidewall surfaces. Form a tunnel oxide layer on the trench sidewall surfaces, the tunnel oxide layer having an outer surface. Form a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Form an interelectrode dielectric layer over the top surface of the floating gate electrode. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode. Form a source line by the step of performing a self-aligned etch followed by a source line implant.

摘要翻译： 通过以下步骤形成硅半导体衬底上的垂直存储器件。 在硅半导体衬底的表面上形成隔离氧化硅结构的阵列。 在硅半导体衬底中在阵列中的氧化硅结构之间形成浮栅沟槽，沟槽具有沟槽侧壁表面。 通过沟槽侧壁表面用阈值注入来掺杂浮栅沟槽的侧壁。 在沟槽侧壁表面上形成隧道氧化物层，隧道氧化物层具有外表面。 在隧道氧化物层的外表面上的沟槽中形成浮栅电极。 衬底中的源极/漏极区域与浮栅电极自对准。 在浮栅电极的顶表面上形成电极间电介质层。 在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极。 通过执行自对准蚀刻，然后进行源极线植入的步骤形成源极线。

公开(公告)号：US06391719B1

公开(公告)日：2002-05-21

申请号：US09575963

申请日：2000-05-23

申请人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11556 ,  H01L21/28273

摘要： A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.

摘要翻译： 形成垂直晶体管存储器件的方法包括以下步骤。 在形成沟槽之前，在行之间形成FOX区域。 在半导体衬底中形成具有侧壁和底部的一组沟槽，其中侧壁具有阈值注入区域。 在衬底的表面附近形成掺杂的漏极区域，并且在沟槽底部的器件的底部中的掺杂源极区域之间具有相反掺杂的沟道区域。 在包括沟槽的衬底上形成隧道氧化物层。 在隧道氧化物层上形成填充沟槽并在沟槽上方延伸的掺杂多晶硅的覆盖厚的浮栅层。 将浮动栅层蚀刻到沟槽顶部的下方。 在浮栅层和隧道氧化物层之上形成由ONO组成的电极间电介质层。 在电极间电介质层上形成掺杂多晶硅的厚度厚的控制栅极层。 将控制栅层图案化为控制栅电极。 形成与控制栅电极的侧壁相邻的间隔物。

公开(公告)号：US5960284A

公开(公告)日：1999-09-28

申请号：US985647

申请日：1997-12-05

申请人： Chrong Jung Lin ,  Shui-Hung Chen ,  Jong Chen ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Shui-Hung Chen ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11556 ,  H01L27/115

摘要： A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. Dope the sidewalls of the floating gate trench with a threshold implant through the trench sidewall surfaces. Form a tunnel oxide layer on the trench sidewall surfaces, the tunnel oxide layer having an outer surface. Form a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Form an interelectrode dielectric layer over the top surface of the floating gate electrode. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode. Form a source line by the step of performing a self-aligned etch followed by a source line implant.

摘要翻译： 通过以下步骤形成硅半导体衬底上的垂直存储器件。 在硅半导体衬底的表面上形成隔离氧化硅结构的阵列。 在硅半导体衬底中在阵列中的氧化硅结构之间形成浮栅沟槽，沟槽具有沟槽侧壁表面。 通过沟槽侧壁表面用阈值注入来掺杂浮栅沟槽的侧壁。 在沟槽侧壁表面上形成隧道氧化物层，隧道氧化物层具有外表面。 在隧道氧化物层的外表面上的沟槽中形成浮栅电极。 衬底中的源极/漏极区域与浮栅电极自对准。 在浮栅电极的顶表面上形成电极间电介质层。 在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极。 通过执行自对准蚀刻，然后进行源极线植入的步骤形成源极线。

公开(公告)号：US6087222A

公开(公告)日：2000-07-11

申请号：US35058

申请日：1998-03-05

申请人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L21/336

CPC分类号： H01L27/11556 ,  H01L21/28273

摘要： A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.