公开(公告)号：US4424561A

公开(公告)日：1984-01-03

申请号：US221854

申请日：1980-12-31

申请人： Philip E. Stanley ,  Richard P. Brown ,  Arthur Peters

发明人： Philip E. Stanley ,  Richard P. Brown ,  Arthur Peters

IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F13/06

CPC分类号： G06F12/0851

摘要： A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.

摘要翻译： 一种在数据处理系统中使用的高速缓存存储器，其中由偶数地址号码识别的数据字与与奇数地址号码相关联的数据字分开存储，以使得能够通过传送 与奇数地址号码相关联的数据字和与偶数地址号码相关联的数据字。

公开(公告)号：US4360869A

公开(公告)日：1982-11-23

申请号：US140639

申请日：1980-04-15

申请人： Philip E. Stanley ,  David E. Cushing ,  Donald R. Taylor

发明人： Philip E. Stanley ,  David E. Cushing ,  Donald R. Taylor

IPC分类号： G06F9/22 ,  G06F9/26

CPC分类号： G06F9/226

摘要： A control store included in a data processing system for storing microinstructions in a plurality of microinstructions storage locations is organized in two parts, an upper bank and a lower bank. The lower bank is directly addressed by a portion of the currently addressed control store word, whereas the upper bank is addressed by use of a multiplexer, with inputs thereto coupled from various logic elements. Apparatus is included to determine which part of the control store will be selected and to allow such determination at a time substantially after the addresses for the first and second parts have been received by the control store. In addition, the elements included in the upper bank are selected to have address propagation time sufficiently faster than the address propagation time of the lower bank to compensate for the additional logic propagation delay introduced by the multiplexer so that the contents of the addressed locations of the upper and lower banks are available for use by the system at substantially the same time.

摘要翻译： 包括在用于存储多个微指令存储位置中的微指令的数据处理系统中的控制存储器被组织在两个部分中，即上部存储体和下部存储体。 低级组由当前寻址的控制存储字的一部分直接寻址，而上部组通过使用多路复用器来寻址，其输入从各种逻辑元件耦合。 包括设备以确定控制存储器的哪个部分将被选择，并且在大多数情况下允许由控制存储器接收到第一和第二部分的地址之后的这种确定。 此外，包括在上层中的元件被选择为具有比下层的地址传播时间足够快的地址传播时间，以补偿由多路复用器引入的附加逻辑传播延迟，使得寻址的位置的内容 大部分同时，系统可以使用上下库。

公开(公告)号：US4524416A

公开(公告)日：1985-06-18

申请号：US430488

申请日：1982-09-30

申请人： Philip E. Stanley ,  Piotr Szorc

发明人： Philip E. Stanley ,  Piotr Szorc

IPC分类号： G06F9/34 ,  G06F15/16

CPC分类号： G06F9/34

摘要： In a data processing system, a stack mechanism creates a stack of operands in a series of memory locations. The memory locations are grouped into stack frames corresponding to the operands included within individual procedures executed by a processing unit of the data processing system. The stack has a maximum number of allocatable storage locations with the actual physical size of the stack being equal to the total number of operands stored therein. The size of the stack is dynamically alterable to conserve usable storage locations in the memory and accessing of operands within a stack frame can be relative to the top or bottom of the stack frame.

摘要翻译： 在数据处理系统中，堆栈机制在一系列存储单元中创建一组操作数。 存储器位置被分组成与由数据处理系统的处理单元执行的各个过程中包括的操作数相对应的堆栈帧。 堆栈具有最大数量的可分配存储位置，堆栈的实际物理大小等于其中存储的操作数的总数。 堆栈的大小可动态地改变以节省存储器中的可用存储位置，并且访问堆栈帧内的操作数可以相对于堆栈帧的顶部或底部。

公开(公告)号：US4445172A

公开(公告)日：1984-04-24

申请号：US221853

申请日：1980-12-31

申请人： Arthur Peters ,  Philip E. Stanley

发明人： Arthur Peters ,  Philip E. Stanley

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0851

摘要： A cache memory including an even data store for storing data words associated with even address numbers and an odd data store for storing data words associated with odd address numbers, a local bus for transferring a low order data word and a high order data word simultaneously from the cache memory to a system element requesting the transfer of a pair of data words through the supplying of a single address number request, and a data steering multiplexer for supplying the data word associated with the memory request number, as outputted from either the odd or even cache data store to the low order data word transfer portion of the local bus and the other of the pair of data words outputted from the odd or even data store to the high order data word transfer portion of the local bus.

摘要翻译： 一种高速缓冲存储器，包括用于存储与偶数地址号码相关联的数据字的偶数数据存储器和用于存储与奇数地址号码相关联的数据字的奇数数据存储器，用于同时从低位数据字传输低位数据字的本地总线和高位数据字 高速缓冲存储器通过提供单个地址号码请求而请求传送一对数据字的系统元件，以及用于提供与存储器请求号相关联的数据字的数据导向复用器，从奇数或 甚至高速缓存数据存储到本地总线的低阶数据字传送部分，以及从奇数或偶数数据存储器输出到本地总线的高位数据字传送部分的一对数据字中的另一个。

公开(公告)号：US4414637A

公开(公告)日：1983-11-08

申请号：US224727

申请日：1981-01-13

申请人： Philip E. Stanley

发明人： Philip E. Stanley

IPC分类号： H03K5/06 ,  H03K5/04 ,  H03K5/159

CPC分类号： H03K5/06

摘要： A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a first delay line coupled to an inverter by using a multitapped second delay line to delay the rectangular wave train by selectable predetermined period. A control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to the rectangular wave train clock cycle period plus the period of the second selected predetermined delay. By serially connecting a multitapped third delay line in series with the second delay line and by providing a first switch to select one of the outputs from said third delay line, the clock cycle period of the clock system may be adjusted. Use of a multitapped delay line for the first delay line and the addition of a second switch for selection among the various delayed signals of the first delay line, enable selective adjustment of clock pulse width.

摘要翻译： 一种用于提供矩形波形或波列的时钟系统，每个波段具有可选择的预定时钟周期周期。 由发生器产生矩形波列，该发生器包括通过使用多重第二延迟线连接到逆变器的第一延迟线，以通过可选择的预定周期延迟矩形波列。 形成控制信号，当馈送到发生器中时，产生具有等于矩形波列时钟周期周期的时钟周期周期加上第二选定预定延迟的周期的第二矩形波列。 通过串联连接与第二延迟线串联的多极化第三延迟线，并且通过提供第一开关来选择来自所述第三延迟线的输出之一，可以调整时钟系统的时钟周期周期。 对于第一延迟线使用多重延迟线和在第一延迟线的各种延迟信号之间添加用于选择的第二开关，使得能够选择性地调整时钟脉冲宽度。

公开(公告)号：US4348724A

公开(公告)日：1982-09-07

申请号：US140643

申请日：1980-04-15

申请人： David E. Cushing ,  Philip E. Stanley

发明人： David E. Cushing ,  Philip E. Stanley

IPC分类号： G06F9/28 ,  G06F9/22 ,  G06F9/26

CPC分类号： G06F9/265

摘要： A data processing system includes a first memory for storing microinstructions in a first plurality of storage locations and second memory for storing microinstructions in a second plurality of storage locations. A central processor executing a series of addressed microinstructions to control the functions performed by this system generates the address of the next microinstruction to be executed in series as well as a next address selection signal. Addressing circuitry concurrently applies the next address generated by the processor to address inputs of each of the first memory and the second memory. After a predetermined delay, either the first memory or the second memory is selected to output an address microinstruction responsive to the value of the next address selection signal.

摘要翻译： 数据处理系统包括用于存储第一多个存储位置中的微指令的第一存储器和用于在第二多个存储位置中存储微指令的第二存储器。 执行一系列寻址微指令以控制由该系统执行的功能的中央处理器产生要串行执行的下一个微指令的地址以及下一个地址选择信号。 寻址电路同时将由处理器产生的下一个地址应用于地址第一存储器和第二存储器中的每一个的输入。 在预定的延迟之后，选择第一存储器或第二存储器以响应于下一个地址选择信号的值来输出地址微指令。