MEMORY APPARATUS HAVING HIERARCHICAL ERROR CORRECTION CODE LAYER

    公开(公告)号:US20200241957A1

    公开(公告)日:2020-07-30

    申请号:US16260058

    申请日:2019-01-28

    IPC分类号: G06F11/10

    摘要: The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N−1 pre-set error correction number(s), and N is a positive integer larger than 1.

    MEMORY STORAGE APPARATUS WITH DYNAMIC DATA REPAIR MECHANISM AND METHOD OF DYNAMIC DATA REPAIR THEREOF

    公开(公告)号:US20190391874A1

    公开(公告)日:2019-12-26

    申请号:US16455769

    申请日:2019-06-28

    IPC分类号: G06F11/10 G06F3/06

    摘要: The disclosure is directed to a memory storage apparatus having a dynamic data repair mechanism. The memory storage apparatus includes a connection interface; a memory array; and a memory control circuit configured at least to: receive, from the connection interface, a write command which includes a user data and an address of the user data; encode the user data as a codeword which includes the user data and parity bits; write the codeword, in a first memory location of the memory array, as a written codeword; perform a read procedure of the written codeword to determine whether the written codeword is erroneously written; and store a redundant codeword of the user data in a second memory location in response to having determined that the written codeword is erroneously written.

    METHOD OF IMPLEMENTING ERROR CORRECTION CODE USED BY MEMORY STORAGE APPARATUS AND MEMORY STORAGE APPARATUS USING THE SAME

    公开(公告)号:US20190294497A1

    公开(公告)日:2019-09-26

    申请号:US16034365

    申请日:2018-07-13

    IPC分类号: G06F11/10 G11C11/56

    摘要: The disclosure is directed to a method and an apparatus for implementing an error correcting code (ECC) used by a memory storage apparatus. In an aspect of the disclosure, the method would include not limited to: receiving a write command having a write address and a write data; reading an existing codeword comprising a predetermined bit sequence; encoding the write data into a new codeword based on a default ECC; flipping at least one bit of the new codeword based on a number of bits required to be changed from the existing codeword to the new codeword; writing the new codeword, wherein in response to every message bit of the new codeword to be flipped once, either an average or a maximum number of parity bits flips of the new codeword is minimized according to a modified ECC which is based on the default ECC.