公开(公告)号：US11088711B2

公开(公告)日：2021-08-10

申请号：US16504349

申请日：2019-07-08

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Chi-Shun Lin ,  Seow Fong Lim ,  Ngatik Cheung

IPC: G06F11/00 ,  G11C29/00 ,  H03M13/35 ,  G06F11/10

Abstract: The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.

公开(公告)号：US20190294496A1

公开(公告)日：2019-09-26

申请号：US15933367

申请日：2018-03-22

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Ming-Huei Shieh ,  Seow Fong Lim ,  Ngatik Cheung ,  Chi-Shun Lin

IPC: G06F11/10 ,  G11C29/42

Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword comprising a first flip bit indicating bit-flipping of the existing codeword and flipping bits of the existing codeword based on the first flip bit; encoding the write data into a new codeword based on a Lien Code by an ECC encoder, and flipping bits of the new codeword based on a number of bits required to be changed from the existing codeword to the new codeword; and writing the new codeword comprising a first flip bit indicating bit-flipping of the new codeword to the write address In addition, a memory storage apparatus using the encoding method based on the Lien Code is provided.

公开(公告)号：US10372535B2

公开(公告)日：2019-08-06

申请号：US15688865

申请日：2017-08-29

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Ming-Huei Shieh ,  Seow-Fong Lim ,  Ngatik Cheung ,  Chi-Shun Lin

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/14 ,  G06F12/02

Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a first data or a second data which is one's complement of the first data; and performing an encoding operation based on the Lien Code by the ECC encoder. The encoding operation includes: if the first data is received, generating a first codeword according to the first data; and if the second data is received, generating a second codeword which is one's complement of the first codeword according to the second data. In addition, a memory storage apparatus using the encoding method based on the Lien Code is also provided.

公开(公告)号：US20180331700A1

公开(公告)日：2018-11-15

申请号：US15592220

申请日：2017-05-11

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Ngatik Cheung

IPC: H03M13/15 ,  H03M13/07 ,  H03M13/00

CPC classification number: H03M13/152 ,  H03M13/07 ,  H03M13/157 ,  H03M13/617

Abstract: An error checking and correcting (ECC) decoder is provided to perform a BCH decoding to decode codeword into decoded data. The ECC decoder includes a syndrome generator circuit, an error locator polynomial circuit, and a decoding circuit. The syndrome generator circuit generates a plurality of syndromes corresponding to the codeword. The error locator polynomial circuit performs an arithmetic operation by using the syndromes to generate a plurality of coefficients in an error locator polynomial. The arithmetic operation includes a plurality of operators, wherein at least one of the operators is a lookup table circuit. The decoding circuit obtains at least one solution to the error locator polynomial with the coefficients and corrects the codeword according to the solution to the error locator polynomial to generate the decoded data.

公开(公告)号：US20180239533A1

公开(公告)日：2018-08-23

申请号：US15441161

申请日：2017-02-23

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Ming-Huei Shieh ,  Chi-Shun Lin

IPC: G06F3/06 ,  G06F11/10 ,  H03M13/37 ,  H03M13/00

CPC classification number: H03M13/6502 ,  G06F11/1048 ,  H03M13/3715

Abstract: A data read method for a memory storage device is provided. The data read method includes: receiving a first read command from a host system for reading first data; calculating an error bit number of the first data; and performing a correction of the first data. If the error bit number is not greater than a predetermined number, finishing the correction of the first data and returning the corrected first data at a pre-defined timing. If the error bit number is greater than a predetermined number, finishing the correction of the first data and returning the corrected first data after the pre-defined timing. In addition, a memory storage device using the data read method is also provided.

公开(公告)号：US09720771B2

公开(公告)日：2017-08-01

申请号：US15389466

申请日：2016-12-23

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Ming-Huei Shieh ,  Chi-Shun Lin

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/12 ,  G11C14/00 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1072 ,  G11C5/148 ,  G11C7/04 ,  G11C7/20 ,  G11C11/005 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/0059 ,  G11C14/0036 ,  G11C14/0045 ,  G11C29/12 ,  G11C29/52

Abstract: A system includes a first nonvolatile memory array, a second nonvolatile memory array, and a memory controller. The memory controller is configured to write an indicator bit to the second nonvolatile memory array, determine whether the indicator bit is valid in response to a power up of the system after a high-temperature event, a received command after a high-temperature event, a predetermined number of power ups, or a power up or received command after each of a predetermined number of high-temperature events, and write data stored in the second nonvolatile memory array to the first nonvolatile memory array when the indicator bit is valid.

公开(公告)号：US11901899B2

公开(公告)日：2024-02-13

申请号：US17239702

申请日：2021-04-26

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Chi-Shun Lin

IPC: G06F7/60 ,  H03K21/40 ,  H03K23/00

CPC classification number: H03K21/403 ,  G06F7/607 ,  H03K23/005

Abstract: A monotonic counter memory system including a counter circuit and a memory circuit is provided. The counter circuit is configured to increase a count by one in response to a clock signal and output a count value of n bits, where n is a positive integer. The memory circuit includes a plurality of memory cells. The memory circuit is configured to store the count value. The stored count value changes one bit at each input count of the clock signal, and a bit switching time of the stored count value are smaller than 2n−1 times.

公开(公告)号：US11114180B1

公开(公告)日：2021-09-07

申请号：US16994670

申请日：2020-08-17

Applicant: Winbond Electronics Corp.

Inventor： Chi-Shun Lin ,  Ngatik Cheung ,  Douk-Hyoun Ryu ,  Ming-Huei Shieh ,  Chuen-Der Lien

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C7/22 ,  G11C7/06 ,  G11C29/12

Abstract: A non-volatile memory device includes a first memory cell array, a first error correction code (ECC) decoder and a controller. The first memory cell array is divided into a first sub-array and a second sub-array by a first address boundary. The first ECC decoder is coupled to the first memory cell array, performs an ECC operation on read-out data from first memory cell array. The controller is coupled to the first memory cell array and the first ECC decoder, adjusts the first address boundary according to a first ECC failure bit number.

公开(公告)号：US10853167B2

公开(公告)日：2020-12-01

申请号：US16260058

申请日：2019-01-28

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Ming-Huei Shieh ,  Chi-Shun Lin ,  Seow Fong Lim ,  Ngatik Cheung

IPC: G06F11/10

Abstract: The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N−1 pre-set error correction number(s), and N is a positive integer larger than 1.

公开(公告)号：US12212338B1

公开(公告)日：2025-01-28

申请号：US18358972

申请日：2023-07-26

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Chi-Shun Lin ,  Ngatik Cheung

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16 ,  G06F13/28 ,  H03M13/11 ,  H03M13/15

Abstract: The disclosure describes a syndrome decoder circuit including: a syndrome computation circuit configured to receive K bits of message bits and P bits of parity bits to calculate S bits of syndrome bits; a X bits weight correction circuit configured to receive multiple sets of first number of bits of the syndrome bits and a first digits of the K bits of message bits to generate a first set of correction masks for the first digits of K bits of message bits; and a X−1 bits weight correction circuit configured to receive multiple sets of second number of bits of the syndrome bits and a second digits of the K bits of message bits to generate a second set of correction masks for the second digits of K bits of message bits. The first number is not equal to the second number.