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公开(公告)号：US20190294496A1
公开(公告)日：2019-09-26
申请号：US15933367
申请日：2018-03-22
Applicant: Winbond Electronics Corp.
Inventor： Chuen-Der Lien , Ming-Huei Shieh , Seow Fong Lim , Ngatik Cheung , Chi-Shun Lin
Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword comprising a first flip bit indicating bit-flipping of the existing codeword and flipping bits of the existing codeword based on the first flip bit; encoding the write data into a new codeword based on a Lien Code by an ECC encoder, and flipping bits of the new codeword based on a number of bits required to be changed from the existing codeword to the new codeword; and writing the new codeword comprising a first flip bit indicating bit-flipping of the new codeword to the write address In addition, a memory storage apparatus using the encoding method based on the Lien Code is provided.
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公开(公告)号：US10372535B2
公开(公告)日：2019-08-06
申请号：US15688865
申请日：2017-08-29
Applicant: Winbond Electronics Corp.
Inventor： Chuen-Der Lien , Ming-Huei Shieh , Seow-Fong Lim , Ngatik Cheung , Chi-Shun Lin
Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a first data or a second data which is one's complement of the first data; and performing an encoding operation based on the Lien Code by the ECC encoder. The encoding operation includes: if the first data is received, generating a first codeword according to the first data; and if the second data is received, generating a second codeword which is one's complement of the first codeword according to the second data. In addition, a memory storage apparatus using the encoding method based on the Lien Code is also provided.
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公开(公告)号：US20180239533A1
公开(公告)日：2018-08-23
申请号：US15441161
申请日：2017-02-23
Applicant: Winbond Electronics Corp.
Inventor： Chuen-Der Lien , Ming-Huei Shieh , Chi-Shun Lin
CPC classification number: H03M13/6502 , G06F11/1048 , H03M13/3715
Abstract: A data read method for a memory storage device is provided. The data read method includes: receiving a first read command from a host system for reading first data; calculating an error bit number of the first data; and performing a correction of the first data. If the error bit number is not greater than a predetermined number, finishing the correction of the first data and returning the corrected first data at a pre-defined timing. If the error bit number is greater than a predetermined number, finishing the correction of the first data and returning the corrected first data after the pre-defined timing. In addition, a memory storage device using the data read method is also provided.
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公开(公告)号：US09720771B2
公开(公告)日：2017-08-01
申请号：US15389466
申请日：2016-12-23
Applicant: Winbond Electronics Corp.
Inventor： Chuen-Der Lien , Ming-Huei Shieh , Chi-Shun Lin
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0655 , G06F3/0679 , G06F3/0688 , G06F11/1072 , G11C5/148 , G11C7/04 , G11C7/20 , G11C11/005 , G11C11/1695 , G11C13/0002 , G11C13/0033 , G11C13/0059 , G11C14/0036 , G11C14/0045 , G11C29/12 , G11C29/52
Abstract: A system includes a first nonvolatile memory array, a second nonvolatile memory array, and a memory controller. The memory controller is configured to write an indicator bit to the second nonvolatile memory array, determine whether the indicator bit is valid in response to a power up of the system after a high-temperature event, a received command after a high-temperature event, a predetermined number of power ups, or a power up or received command after each of a predetermined number of high-temperature events, and write data stored in the second nonvolatile memory array to the first nonvolatile memory array when the indicator bit is valid.
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公开(公告)号：US10811092B1
公开(公告)日：2020-10-20
申请号：US16542306
申请日：2019-08-16
Applicant: Winbond Electronics Corp.
Inventor： Chi-Shun Lin , Chuen-Der Lien , Douk-Hyoun Ryu , Ming-Huei Shieh , Seow Fong Lim
Abstract: The disclosure is directed to a RRAM having a plurality of 1TnR structures. In an aspect, the disclosure provides a RRAM including a plurality of 1TnR structures which includes a first 1TnR structure which includes a first transistor having a first gate terminal connected to a first word line, a first drain terminal, and a first source terminal connected to a source line, wherein the source line is connected to each of the plurality of 1TnR structures; and a first N parallel resistors group including a first resistor and a second resistor which are connected to the first drain terminal and connected to each other in parallel, wherein the first resistor is connected to a first bit line, the second resistor is connected to a second bit line, and N is an integer greater than one.
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Patent Agency Ranking
公开(公告)号：US20190050285A1
公开(公告)日：2019-02-14
申请号：US15674520
申请日：2017-08-11
Applicant: Winbond Electronics Corp.
Inventor： Chi-Shun Lin , Ming-Huei Shieh
IPC: G06F11/10
CPC classification number: G06F11/1044 , G06F11/1048
Abstract: A data write method for writing data is provided. The data writing method is adapted to a memory controller adopting an ECC scheme and includes: encoding the data to generate a codeword; writing the codeword into the memory array according to a first write condition; and performing a verify operation. The step of performing the verify operation includes: reading the codeword from the memory array; comparing the read codeword with the codeword and obtaining an error bit number of the read codeword; decoding the read codeword to generate a decoded data by an ECC decoder; comparing the decoded data with the data; and comparing the error bit number of the read codeword with a pass threshold if the decoded data is identical to the data. If the error bit number of the read codeword is greater than the pass threshold, the data write method further comprises writing the codeword into the memory array according to a second write condition, where the second write condition is different from the first write condition. In addition, a memory storage device using the data write method is also provided.
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公开(公告)号：US09798481B1
公开(公告)日：2017-10-24
申请号：US15182612
申请日：2016-06-15
Applicant: Winbond Electronics Corp.
Inventor： Ming-Huei Shieh , Chuen-Der Lien , Chi-Shun Lin
CPC classification number: G11C13/0061 , G11C5/04 , G11C13/0069 , G11C2013/0076 , G11C2013/0083 , H05K1/00
Abstract: A memory system and operating method thereof are provided. The non-volatile memory array is configured to store data. The controller is coupled to the non-volatile memory array. The memory controller is configured to provide a special write operation to write the data in the non-volatile memory array before a board mount operation is applied, and provide a regular write operation to write the data in the non-volatile memory array after the board mount operation is applied. A read margin provided by the special write operation is larger than a read margin provided by the regular write operation.
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公开(公告)号：US09563505B2
公开(公告)日：2017-02-07
申请号：US14721030
申请日：2015-05-26
Applicant: Winbond Electronics Corp.
Inventor： Chuen-Der Lien , Ming-Huei Shieh , Chi-Shun Lin
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0655 , G06F3/0679 , G06F3/0688 , G06F11/1072 , G11C5/148 , G11C7/04 , G11C7/20 , G11C11/005 , G11C11/1695 , G11C13/0002 , G11C13/0033 , G11C13/0059 , G11C14/0036 , G11C14/0045 , G11C29/12 , G11C29/52
Abstract: A system includes a first nonvolatile memory array, a second nonvolatile memory array, and a memory controller. The memory controller is configured to write an indicator bit to the second nonvolatile memory array, determine whether the indicator bit is valid in response to a power up of the system after a high-temperature event, a received command after a high-temperature event, a predetermined number of power ups, or a power up or received command after each of a predetermined number of high-temperature events, and write data stored in the second nonvolatile memory array to the first nonvolatile memory array when the indicator bit is valid.
Abstract translation: 系统包括第一非易失性存储器阵列，第二非易失性存储器阵列和存储器控制器。 存储器控制器被配置为向第二非易失性存储器阵列写入指示符位，响应于高温事件之后的系统的上电，高温事件之后的接收命令，确定指示符位是否有效， 预定数量的电源ups，或者在预定数量的高温事件中的每一个之后的上电或接收命令，以及当指示符位有效时将存储在第二非易失性存储器阵列中的数据写入第一非易失性存储器阵列。
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公开(公告)号：US20150269993A1
公开(公告)日：2015-09-24
申请号：US14219003
申请日：2014-03-19
Applicant: Winbond Electronics Corp.
Inventor： Ming-Huei Shieh , Yuan-Mou Su , Hua-Yu Su , Young-Tae Kim , Douk-Hyoun Ryu
IPC: G11C13/00
CPC classification number: G11C13/0002 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/79
Abstract: A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first transistor, a second transistor, a first resistor and a second resistor. First and second terminals of the first transistor are respectively coupled to a first bit line and a reference voltage. First and second terminals of the second transistor are respectively coupled to a second bit line and the reference voltage. The first resistor is serially coupled on a coupling path between the first terminal of the first transistor and the first bit line, or on a coupling path between the second terminal of the first transistor and the reference voltage. The second resistor is serially coupled on a coupling path between the first terminal of the second transistor coupled and the second bit line, or on a coupling path between the second terminal of the second transistor and the reference voltage.
Abstract translation: 提供了一种电阻式存储装置及其存储单元。 电阻存储单元包括第一晶体管，第二晶体管，第一电阻器和第二电阻器。 第一晶体管的第一和第二端子分别耦合到第一位线和参考电压。 第二晶体管的第一和第二端子分别耦合到第二位线和参考电压。 第一电阻器串联耦合在第一晶体管的第一端和第一位线之间的耦合路径上，或者在第一晶体管的第二端与参考电压之间的耦合路径上。 第二电阻串联耦合在第二晶体管耦合的第一端和第二位线之间的耦合路径上，或者在第二晶体管的第二端与耦合路径之间。
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公开(公告)号：US11114180B1
公开(公告)日：2021-09-07
申请号：US16994670
申请日：2020-08-17
Applicant: Winbond Electronics Corp.
Inventor： Chi-Shun Lin , Ngatik Cheung , Douk-Hyoun Ryu , Ming-Huei Shieh , Chuen-Der Lien
Abstract: A non-volatile memory device includes a first memory cell array, a first error correction code (ECC) decoder and a controller. The first memory cell array is divided into a first sub-array and a second sub-array by a first address boundary. The first ECC decoder is coupled to the first memory cell array, performs an ECC operation on read-out data from first memory cell array. The controller is coupled to the first memory cell array and the first ECC decoder, adjusts the first address boundary according to a first ECC failure bit number.
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