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公开(公告)号：US10714157B1
公开(公告)日：2020-07-14
申请号：US16551752
申请日：2019-08-27
发明人： Ming-Che Lin , He-Hsuan Chao , Ping-Kun Wang , Seow Fong Lim , Ngatik Cheung , Chia-Wen Cheng
IPC分类号： G11C7/10
摘要： A non-volatile memory and a reset method thereof are provided. The reset method includes: performing a first reset operation on a plurality of memory cells; recording a plurality of first verifying currents respectively corresponding to a plurality of first failure memory cells; performing a second reset operation on the first failure memory cells, and verifying second failure memory cells to obtain a plurality of second verifying currents; setting a first voltage modify flag according to a plurality of first ratios between the first verifying currents and the respectively corresponding second verifying currents; and adjusting a reset voltage for performing the first reset operation and the second reset operation according to the first voltage modify flag.
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公开(公告)号：US10262732B2
公开(公告)日：2019-04-16
申请号：US15960569
申请日：2018-04-24
发明人： Seow Fong Lim , Chi-Shun Lin , Douk-Hyoun Ryu , Ngatik Cheung
IPC分类号： H03K19/003 , G11C13/00 , H03K19/00
摘要： This disclosure introduces a programmable array logic (PAL) circuit and a method which are capable of preventing a read disturbance effect on memory cells of the PAL circuit. The PAL circuit comprises a memory array coupled to a plurality of input lines and a plurality of source lines, a plurality of input transition detection (ITD) circuits, a pulse generator and a plurality of sense amplifiers. The plurality of ITD circuits detect a transition in level of the plurality of input signals in the input lines. The pulse generator generates an enable signal according to the transition in level of the input signals. The sense amplifiers are enabled to sense the voltage levels of the source lines when the transition in levels of the input signals is detected, and the sense amplifiers are disabled when no transition in levels of the input signals is detected.
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公开(公告)号：US20240347118A1
公开(公告)日：2024-10-17
申请号：US18319501
申请日：2023-05-18
CPC分类号： G11C16/3459 , G11C16/102
摘要： A memory device and an enhance programming method thereof are provided. The enhance programming method includes: performing program and verifying operations on a plurality of memory cell groups of a memory division, where each of the memory cell group corresponds to at least one byte; calculating a programming time for completing program operation of each of the memory cell groups; setting an indication flag when the programming time is larger than a preset threshold value; and, when the indication flag is in a setting state, increasing at least one of a plurality of program operation parameters, and performing an enhancement programming operation on the memory cell groups of the memory division.
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公开(公告)号：US11114180B1
公开(公告)日：2021-09-07
申请号：US16994670
申请日：2020-08-17
发明人： Chi-Shun Lin , Ngatik Cheung , Douk-Hyoun Ryu , Ming-Huei Shieh , Chuen-Der Lien
摘要： A non-volatile memory device includes a first memory cell array, a first error correction code (ECC) decoder and a controller. The first memory cell array is divided into a first sub-array and a second sub-array by a first address boundary. The first ECC decoder is coupled to the first memory cell array, performs an ECC operation on read-out data from first memory cell array. The controller is coupled to the first memory cell array and the first ECC decoder, adjusts the first address boundary according to a first ECC failure bit number.
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公开(公告)号：US10853167B2
公开(公告)日：2020-12-01
申请号：US16260058
申请日：2019-01-28
发明人： Chuen-Der Lien , Ming-Huei Shieh , Chi-Shun Lin , Seow Fong Lim , Ngatik Cheung
IPC分类号： G06F11/10
摘要： The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N−1 pre-set error correction number(s), and N is a positive integer larger than 1.
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公开(公告)号：US20190043575A1
公开(公告)日：2019-02-07
申请号：US15960569
申请日：2018-04-24
发明人： Seow Fong Lim , Chi-Shun Lin , Douk-Hyoun Ryu , Ngatik Cheung
IPC分类号： G11C13/00 , H03K19/003 , H03K19/00
摘要： This disclosure introduces a programmable array logic (PAL) circuit and a method which are capable of preventing a read disturbance effect on memory cells of the PAL circuit. The PAL circuit comprises a memory array coupled to a plurality of input lines and a plurality of source lines, a plurality of input transition detection (ITD) circuits, a pulse generator and a plurality of sense amplifiers. The plurality of ITD circuits detect a transition in level of the plurality of input signals in the input lines. The pulse generator generates an enable signal according to the transition in level of the input signals. The sense amplifiers are enabled to sense the voltage levels of the source lines when the transition in levels of the input signals is detected, and the sense amplifiers are disabled when no transition in levels of the input signals is detected.
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公开(公告)号：US11088711B2
公开(公告)日：2021-08-10
申请号：US16504349
申请日：2019-07-08
发明人： Chuen-Der Lien , Chi-Shun Lin , Seow Fong Lim , Ngatik Cheung
摘要： The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.
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公开(公告)号：US20190294496A1
公开(公告)日：2019-09-26
申请号：US15933367
申请日：2018-03-22
发明人： Chuen-Der Lien , Ming-Huei Shieh , Seow Fong Lim , Ngatik Cheung , Chi-Shun Lin
摘要： An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword comprising a first flip bit indicating bit-flipping of the existing codeword and flipping bits of the existing codeword based on the first flip bit; encoding the write data into a new codeword based on a Lien Code by an ECC encoder, and flipping bits of the new codeword based on a number of bits required to be changed from the existing codeword to the new codeword; and writing the new codeword comprising a first flip bit indicating bit-flipping of the new codeword to the write address In addition, a memory storage apparatus using the encoding method based on the Lien Code is provided.
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公开(公告)号：US10372535B2
公开(公告)日：2019-08-06
申请号：US15688865
申请日：2017-08-29
发明人： Chuen-Der Lien , Ming-Huei Shieh , Seow-Fong Lim , Ngatik Cheung , Chi-Shun Lin
摘要： An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a first data or a second data which is one's complement of the first data; and performing an encoding operation based on the Lien Code by the ECC encoder. The encoding operation includes: if the first data is received, generating a first codeword according to the first data; and if the second data is received, generating a second codeword which is one's complement of the first codeword according to the second data. In addition, a memory storage apparatus using the encoding method based on the Lien Code is also provided.
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公开(公告)号：US20180331700A1
公开(公告)日：2018-11-15
申请号：US15592220
申请日：2017-05-11
发明人： Chuen-Der Lien , Ngatik Cheung
CPC分类号： H03M13/152 , H03M13/07 , H03M13/157 , H03M13/617
摘要： An error checking and correcting (ECC) decoder is provided to perform a BCH decoding to decode codeword into decoded data. The ECC decoder includes a syndrome generator circuit, an error locator polynomial circuit, and a decoding circuit. The syndrome generator circuit generates a plurality of syndromes corresponding to the codeword. The error locator polynomial circuit performs an arithmetic operation by using the syndromes to generate a plurality of coefficients in an error locator polynomial. The arithmetic operation includes a plurality of operators, wherein at least one of the operators is a lookup table circuit. The decoding circuit obtains at least one solution to the error locator polynomial with the coefficients and corrects the codeword according to the solution to the error locator polynomial to generate the decoded data.
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