公开(公告)号：US11088711B2

公开(公告)日：2021-08-10

申请号：US16504349

申请日：2019-07-08

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Chi-Shun Lin ,  Seow Fong Lim ,  Ngatik Cheung

IPC: G06F11/00 ,  G11C29/00 ,  H03M13/35 ,  G06F11/10

Abstract: The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.

公开(公告)号：US20210005255A1

公开(公告)日：2021-01-07

申请号：US16460995

申请日：2019-07-02

Applicant: Winbond Electronics Corp.

Inventor： He-Hsuan Chao ,  Ping-Kun Wang ,  Seow Fong Lim ,  Norio Hattori ,  Chien-Min Wu ,  Chih-Hua Hung

IPC: G11C13/00

Abstract: A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.

公开(公告)号：US10439829B1

公开(公告)日：2019-10-08

申请号：US16264698

申请日：2019-02-01

Applicant: Winbond Electronics Corp.

Inventor： Lih-Wei Lin ,  Chi-Shun Lin ,  Seow Fong Lim

IPC: H04L9/32 ,  H04L9/08 ,  G11C13/00

Abstract: A physical unclonable function code generating method includes: providing a plurality of non-volatile memory cell pairs including a first non-volatile memory cell and a second non-volatile memory cell; comparing an initial state of the first non-volatile memory cell with an initial state of the second non-volatile memory cell, and generating a first physical unclonable function code according to a comparison result of the state; calculating a formation ratio difference of a logical level in the first physical unclonable function code; and adjusting the formation ratio difference by interactively performing forming operations on the first non-volatile memory cell and the second non-volatile memory cell when the formation ratio difference is greater than or equal to a ratio threshold.

公开(公告)号：US20190294496A1

公开(公告)日：2019-09-26

申请号：US15933367

申请日：2018-03-22

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Ming-Huei Shieh ,  Seow Fong Lim ,  Ngatik Cheung ,  Chi-Shun Lin

IPC: G06F11/10 ,  G11C29/42

Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword comprising a first flip bit indicating bit-flipping of the existing codeword and flipping bits of the existing codeword based on the first flip bit; encoding the write data into a new codeword based on a Lien Code by an ECC encoder, and flipping bits of the new codeword based on a number of bits required to be changed from the existing codeword to the new codeword; and writing the new codeword comprising a first flip bit indicating bit-flipping of the new codeword to the write address In addition, a memory storage apparatus using the encoding method based on the Lien Code is provided.

公开(公告)号：US20190088321A1

公开(公告)日：2019-03-21

申请号：US16118445

申请日：2018-08-31

Applicant: Winbond Electronics Corp.

Inventor： Lih-Wei Lin ,  Tsung-Huan Tsai ,  Chi-Shun Lin ,  Seow Fong Lim

IPC: G11C13/00

Abstract: An operating method of a resistive memory element includes: performing a thermal step on the resistive memory element; performing a set and reset cycle operation on the resistive memory element to increase a read margin of the resistive memory element after a thermal step; and determining whether the resistive memory element passes a read margin verification.

公开(公告)号：US10853167B2

公开(公告)日：2020-12-01

申请号：US16260058

申请日：2019-01-28

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Ming-Huei Shieh ,  Chi-Shun Lin ,  Seow Fong Lim ,  Ngatik Cheung

IPC: G06F11/10

Abstract: The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N−1 pre-set error correction number(s), and N is a positive integer larger than 1.

公开(公告)号：US20190043575A1

公开(公告)日：2019-02-07

申请号：US15960569

申请日：2018-04-24

Applicant: Winbond Electronics Corp.

Inventor： Seow Fong Lim ,  Chi-Shun Lin ,  Douk-Hyoun Ryu ,  Ngatik Cheung

IPC: G11C13/00 ,  H03K19/003 ,  H03K19/00

Abstract: This disclosure introduces a programmable array logic (PAL) circuit and a method which are capable of preventing a read disturbance effect on memory cells of the PAL circuit. The PAL circuit comprises a memory array coupled to a plurality of input lines and a plurality of source lines, a plurality of input transition detection (ITD) circuits, a pulse generator and a plurality of sense amplifiers. The plurality of ITD circuits detect a transition in level of the plurality of input signals in the input lines. The pulse generator generates an enable signal according to the transition in level of the input signals. The sense amplifiers are enabled to sense the voltage levels of the source lines when the transition in levels of the input signals is detected, and the sense amplifiers are disabled when no transition in levels of the input signals is detected.

公开(公告)号：US20210141689A1

公开(公告)日：2021-05-13

申请号：US16679292

申请日：2019-11-11

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Ming-Huei Shieh ,  Chi-Shun Lin ,  Seow Fong Lim ,  Ngatik Cheung

IPC: G06F11/10

Abstract: A memory device and a multiple cells error correction in a memory cell is provided. The memory device includes a plurality of memory cells and a memory control circuit. Each of the memory cells includes a first type physical cell and a second type physical cell. The memory control circuit is coupled to each of the memory cells. The memory control circuit writes a writing data into the first type physical cell and verifies the data stored in the first type physical cell is same as the writing data or not. The writing data is set and processed by performing a write operation. The memory control circuit writes the writing data into the second type physical cell when the data stored in the first type physical cell is not same as the writing data.

公开(公告)号：US10514980B2

公开(公告)日：2019-12-24

申请号：US15933367

申请日：2018-03-22

Applicant: Winbond Electronics Corp.

Inventor： Chuen-Der Lien ,  Ming-Huei Shieh ,  Seow Fong Lim ,  Ngatik Cheung ,  Chi-Shun Lin

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/42

Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword comprising a first flip bit indicating bit-flipping of the existing codeword and flipping bits of the existing codeword based on the first flip bit; encoding the write data into a new codeword based on a Lien Code by an ECC encoder, and flipping bits of the new codeword based on a number of bits required to be changed from the existing codeword to the new codeword; and writing the new codeword comprising a first flip bit indicating bit-flipping of the new codeword to the write address In addition, a memory storage apparatus using the encoding method based on the Lien Code is provided.

公开(公告)号：US10811092B1

公开(公告)日：2020-10-20

申请号：US16542306

申请日：2019-08-16

Applicant: Winbond Electronics Corp.

Inventor： Chi-Shun Lin ,  Chuen-Der Lien ,  Douk-Hyoun Ryu ,  Ming-Huei Shieh ,  Seow Fong Lim

IPC: G11C13/00 ,  H01L27/24

Abstract: The disclosure is directed to a RRAM having a plurality of 1TnR structures. In an aspect, the disclosure provides a RRAM including a plurality of 1TnR structures which includes a first 1TnR structure which includes a first transistor having a first gate terminal connected to a first word line, a first drain terminal, and a first source terminal connected to a source line, wherein the source line is connected to each of the plurality of 1TnR structures; and a first N parallel resistors group including a first resistor and a second resistor which are connected to the first drain terminal and connected to each other in parallel, wherein the first resistor is connected to a first bit line, the second resistor is connected to a second bit line, and N is an integer greater than one.