公开(公告)号：US09825632B1

公开(公告)日：2017-11-21

申请号：US15228981

申请日：2016-08-04

Applicant: Xilinx, Inc.

Inventor： Pierre Maillard ,  Michael J. Hart ,  Praful Jain ,  Robert I. Fu

IPC: H03K19/003 ,  H03K19/177

CPC classification number: H03K19/00315 ,  H03K19/17728 ,  H03K19/1776

Abstract: A circuit for preventing multi-bit upsets induced by single event transients is described. The circuit comprises a clock generator configured to generate a first clock signal and a second clock signal; a first memory element configured to receive a first input signal and generate a first output signal, the first memory element having a first clock input configured to receive the first clock signal; and a second memory element configured to receive the first output signal and generate a second output signal, the second memory element having a second clock input configured to receive the second clock signal; wherein the first clock signal is the same as the second clock signal. A method of preventing multi-bit upsets induced by single event transients is also described.

公开(公告)号：US09793899B1

公开(公告)日：2017-10-17

申请号：US15382385

申请日：2016-12-16

Applicant: Xilinx, Inc.

Inventor： Pierre Maillard ,  Jue Arver ,  Michael J. Hart ,  John K. Jennings

IPC: H03K19/003 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K19/0033

Abstract: The disclosed IC includes a load circuit and a temperature sensor circuit. The temperature sensor circuit measures temperature of the IC and stores temperature data in a register. An SEL mitigation circuit monitors the IC for a temperature change indicative of an SEL. A temperature change greater than a threshold over a time interval is indicative of an SEL. The SEL mitigation circuit is configured to reduce voltage applied to the IC to a voltage level that clears an SEL in the IC in response to a temperature change exceeding the threshold and to increase voltage applied to the load circuit after the reduction in voltage.

公开(公告)号：US20160049940A1

公开(公告)日：2016-02-18

申请号：US14458017

申请日：2014-08-12

Applicant: Xilinx, Inc.

Inventor： Praful Jain ,  Michael J. Hart

IPC: H03K19/0185 ,  H01L27/118 ,  H03K19/177

CPC classification number: H03K19/018571 ,  H01L27/11803 ,  H03K19/1737 ,  H03K19/17736 ,  H03K19/1776

Abstract: An exemplary interconnect circuit for a programmable integrated circuit (IC) includes an input terminal coupled to receive from a node in the programmable IC, an output terminal coupled to transmit towards another node in the programmable IC, first and second control terminals coupled to receive from a memory cell of the programmable IC, and a complementary metal oxide semiconductor (CMOS) pass-gate coupled between the input terminal and the output terminal and to the first and second control terminals. The CMOS pass-gate includes a P-channel transistor configured with a low threshold voltage for a CMOS process used to fabricate the programmable IC.

Abstract translation: 用于可编程集成电路（IC）的示例性互连电路包括耦合以从可编程IC中的节点接收的输入端子，耦合到朝向可编程IC中的另一节点发送的输出端子，耦合以从可编程集成电路 可编程IC的存储单元和耦合在输入端子和输出端子之间的互补金属氧化物半导体（CMOS）通过栅极以及耦合到第一和第二控制端子。 CMOS通过栅极包括配置有用于制造可编程IC的CMOS工艺的低阈值电压的P沟道晶体管。

公开(公告)号：US09236353B2

公开(公告)日：2016-01-12

申请号：US13686553

申请日：2012-11-27

Applicant: Xilinx, Inc.

Inventor： Praful Jain ,  James Karp ,  Michael J. Hart

IPC: H01L27/092 ,  H01L23/552 ,  H01L21/02 ,  G11C11/412 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L23/552 ,  G11C11/4125 ,  H01L21/02697 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors.

Abstract translation: 描述了具有改善的辐射抗扰性的集成电路。 集成电路包括基板; 在衬底上形成的P阱，并具有存储单元的N型晶体管; 和形成在衬底上并具有存储单元的P型晶体管的N阱; 其中所述N阱具有用于容纳所述P型晶体管的最小尺寸。

公开(公告)号：US11177654B1

公开(公告)日：2021-11-16

申请号：US16152011

申请日：2018-10-04

Applicant: Xilinx, Inc.

Inventor： John K. Jennings ,  James Karp ,  Michael J. Hart

IPC: H02H9/04 ,  H02H1/00 ,  H01L27/02

Abstract: Examples described herein provide a circuit and methods for self-testing to detect damage to a device, which damage may be caused by an Electro-Static Discharge (ESD) event. In an example, an integrated circuit includes an input/output circuit, an ESD protection circuit, and a system monitor. The input/output circuit has an input/output node. The ESD protection circuit is connected to the input/output node. The system monitor has a driving/measurement node selectively connectable to the input/output node. The system monitor is configured to drive and measure a voltage of the driving/measurement node. The system monitor is further configured to determine, based on driving and measuring the voltage of the driving/measurement node, whether a damaged device is present. The damaged device is in the input/output circuit or the ESD protection circuit.

公开(公告)号：US10811493B2

公开(公告)日：2020-10-20

申请号：US16109273

申请日：2018-08-22

Applicant: Xilinx, Inc.

Inventor： James Karp ,  Michael J. Hart

IPC: H01L29/06 ,  H01L27/092 ,  H01L27/06

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.

公开(公告)号：US10033388B1

公开(公告)日：2018-07-24

申请号：US15465402

申请日：2017-03-21

Applicant: Xilinx, Inc.

Inventor： Mini Rawat ,  Pierre Maillard ,  Michael J. Hart

IPC: H03K19/177 ,  H03K19/00

Abstract: An integrated circuit enables the selection of a circuit. According to one implementation, a plurality of redundant circuits provide a predetermined function and a voltage sensor may be coupled to receive a reference voltage. A selection circuit may be coupled to the voltage sensor and the reference voltage, wherein the selection circuit selects one of the plurality of redundant circuits to be implemented in the integrated circuit based upon a detected voltage of the reference voltage of the reference voltage.

公开(公告)号：US09831218B1

公开(公告)日：2017-11-28

申请号：US15480258

申请日：2017-04-05

Applicant: Xilinx, Inc.

Inventor： James Karp ,  Michael J. Hart

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/60 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06572

Abstract: Embodiments herein describe techniques for wafer to wafer stacking of integrated circuit chips (e.g., dice) to form stacked IC devices. In one example, a stacked IC device is provided that includes a first wafer, a second wafer, and first conductive bridge. The second wafer is stacked on and secured to the first wafer. The second wafer has a plurality of IC dice that are communicatively coupled to a plurality of IC dice formed on the first wafer. The first conductive bridge has a first end that is sandwiched between the first and second wafers. The first conductive bridge shorts exposed pads of dice formed in the exclusion zones of the first and second wafers.

公开(公告)号：US20140145293A1

公开(公告)日：2014-05-29

申请号：US13686553

申请日：2012-11-27

Applicant: Xilinx, Inc.

Inventor： Praful Jain ,  James Karp ,  Michael J. Hart

IPC: H01L23/552 ,  H01L21/02

CPC classification number: H01L23/552 ,  G11C11/4125 ,  H01L21/02697 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors.

Abstract translation: 描述了具有改善的辐射抗扰性的集成电路。 集成电路包括基板; 在衬底上形成的P阱，并具有存储单元的N型晶体管; 和形成在衬底上并具有存储单元的P型晶体管的N阱; 其中所述N阱具有用于容纳所述P型晶体管的最小尺寸。