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    Embedded shield for protection of memory cells
    1.
    发明授权
    Embedded shield for protection of memory cells 有权

    公开(公告)号：US11508667B1

    公开(公告)日：2022-11-22

    申请号：US16717708

    申请日：2019-12-17

    Applicant: XILINX, INC.

    Inventor： James Karp ,  Yan Wang

    IPC: H01L23/552 ,  H01L23/528 ,  H01L23/50

    Abstract: Some examples described herein provide for a shield in an integrated circuit (IC) structure for memory protection. In an example, an IC structure includes a semiconductor material, an interconnect structure, and a shield. The semiconductor material has a protected region. Devices are disposed in a first side of the semiconductor material in the protected region. The interconnect structure is disposed on the first side of the semiconductor material. The interconnect structure interconnects the devices in the protected region. The shield is disposed on a second side of the semiconductor material opposite from the first side of the semiconductor material. The shield is positioned aligned with the protected region.

    INTEGRATED CIRCUIT DEVICE WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION
    2.
    发明申请
    INTEGRATED CIRCUIT DEVICE WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION 审中-公开

    公开(公告)号：US20200343237A1

    公开(公告)日：2020-10-29

    申请号：US16392460

    申请日：2019-04-23

    Applicant: Xilinx, Inc.

    Inventor： James Karp

    IPC: H01L27/02 ,  H01L23/31 ,  H01L23/60 ,  H01L25/065

    Abstract: Disclosed herein are integrated circuit devices and and methods for fabricating the same that include at least one non-I/O die having ESD protection circuitry. The ESD protection circuitry disclosed herein may also be utilized in I/O dies. In one example, an integrated circuit device includes a die having a first body. First and second contact pads are exposed to a surface of the first body. The first contact pad is configured to connect to a first supply voltage. The second contact pad is configured to connect to a second supply voltage or ground. A first charge-sensitive circuitry formed in the first body is coupled between the first and second contact pads. A first RC clamp formed in the first body is coupled between the first and second contact pads. The first RC clamp includes at least two BigFETs coupled between the first and second contact pads, and a trigger circuitry coupled in parallel to gate terminals of the at least two BigFETs.

    On chip detection of electrical overstress events
    4.
    发明授权
    On chip detection of electrical overstress events 有权
    片上检测电应力事件

    公开(公告)号：US09575111B1

    公开(公告)日：2017-02-21

    申请号：US13942626

    申请日：2013-07-15

    Applicant: Xilinx, Inc.

    Inventor： James Karp ,  Michael J. Hart ,  John K. Jennings

    IPC: H02H3/00 ,  G01R31/26 ,  H02H3/20 ,  H03K17/08

    CPC classification number: G01R31/26 ,  H02H3/00 ,  H02H3/20 ,  H03K17/08 ,  H03K19/00369

    Abstract: A system configured for detecting electrical overstress events within an integrated circuit includes a comparator configured to determine whether a monitored voltage level of a monitored signal exceeds an overstress reference voltage level. The overstress reference voltage level is a predetermined amount of voltage above a nominal voltage level for the monitored signal. The system further includes a write circuit coupled to an output of the comparator. The write circuit is configured to indicate an occurrence of an electrical overstress event within the integrated circuit responsive to the comparator determining that the monitored voltage level exceeds the overstress reference voltage level.

    Abstract translation: 配置用于检测集成电路内的过电压事件的系统包括：比较器，被配置为确定所监视的信号的监测电压电平是否超过过应力参考电压电平。 超应力参考电压电平是高于监视信号的额定电压电平的预定量的电压。 该系统还包括耦合到比较器的输出的写入电路。 写电路被配置为响应于比较器确定监视的电压电平超过过应力参考电压电平来指示集成电路内的电应力事件的发生。

    Integrated circuit device with electrostatic discharge (ESD) protection
    6.
    发明授权
    Integrated circuit device with electrostatic discharge (ESD) protection 有权

    公开(公告)号：US11114429B2

    公开(公告)日：2021-09-07

    申请号：US16392460

    申请日：2019-04-23

    Applicant: Xilinx, Inc.

    Inventor： James Karp

    IPC: H01L27/02 ,  H01L25/065 ,  H01L23/60 ,  H01L23/31

    Abstract: Disclosed herein are integrated circuit devices and methods for fabricating the same that include at least one non-I/O die having ESD protection circuitry. The ESD protection circuitry disclosed herein may also be utilized in I/O dies. In one example, an integrated circuit device includes a die having a first body. First and second contact pads are exposed to a surface of the first body. The first contact pad is configured to connect to a first supply voltage. The second contact pad is configured to connect to a second supply voltage or ground. A first charge-sensitive circuitry formed in the first body is coupled between the first and second contact pads. A first RC clamp formed in the first body is coupled between the first and second contact pads. The first RC clamp includes at least two BigFETs coupled between the first and second contact pads, and a trigger circuitry coupled in parallel to gate terminals of the at least two BigFETs.

    SINGLE EVENT LATCH-UP (SEL) MITIGATION TECHNIQUES
    7.
    发明申请
    SINGLE EVENT LATCH-UP (SEL) MITIGATION TECHNIQUES 审中-公开

    公开(公告)号：US20200066713A1

    公开(公告)日：2020-02-27

    申请号：US16110894

    申请日：2018-08-23

    Applicant: Xilinx, Inc.

    Inventor： Michael J. Hart ,  James Karp ,  Mohammed Fakhruddin ,  Pierre Maillard

    IPC: H01L27/06 ,  H01L27/02 ,  H01L29/73 ,  H01L29/78 ,  H01L49/02

    Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

    MITIGATION FOR FINFET TECHNOLOGY USING DEEP ISOLATION
    8.
    发明申请
    MITIGATION FOR FINFET TECHNOLOGY USING DEEP ISOLATION 审中-公开

    公开(公告)号：US20190280086A1

    公开(公告)日：2019-09-12

    申请号：US15917206

    申请日：2018-03-09

    Applicant: Xilinx, Inc.

    Inventor： James Karp ,  Michael J. Hart

    IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

    Abstract: FinFET, P-N junctions and methods for forming the same are described herein. In one example, a FinFET transistor is described that includes a fin having a channel region wrapped by a gate, the channel region connecting a source and a drain. A first isolation layer is disposed on a first side of the in and a second isolation layer is disposed on a second side of the fin, where the second side is opposite of the first side. The second oxide isolation layer has a thickness greater than a thickness of the first isolation layer.

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