公开(公告)号：US07700479B2

公开(公告)日：2010-04-20

申请号：US11593286

申请日：2006-11-06

申请人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

发明人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC分类号： H01L21/4763

CPC分类号： H01L21/02063 ,  H01L21/76807 ,  H01L21/76814

摘要： A method for fabricating an integrated circuit includes providing a substrate, forming a low-k dielectric layer over the substrate, etching the low-k dielectric layer to form an opening in the low-k dielectric layer wherein an underlying metal is exposed through the opening, performing a remote plasma treatment to the substrate wherein a plasma used for the remote plasma treatment is generated from a plasma generator separated from a chamber in which the substrate is located, forming a diffusion barrier layer in the opening, and filling the opening with a conductive material. The method preferably includes an in-situ plasma treatment in a same chamber as the step of etching the low-k dielectric layer.

摘要翻译： 一种用于制造集成电路的方法包括提供衬底，在衬底上形成低k电介质层，蚀刻低k电介质层以在低k电介质层中形成开口，其中下面的金属通过开口暴露 对基板执行远程等离子体处理，其中用于远程等离子体处理的等离子体从与其中所述基板所在的室分离的等离子体发生器产生，在该开口中形成扩散阻挡层，并且在该开口中填充该开口 导电材料。 该方法优选包括在与蚀刻低k电介质层的步骤相同的室中的原位等离子体处理。

公开(公告)号：US07612451B2

公开(公告)日：2009-11-03

申请号：US11486893

申请日：2006-07-13

申请人： Chih-Chao Shih ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

发明人： Chih-Chao Shih ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76856 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, and a damascene structure in the opening. The damascene structure includes a metallic barrier layer in the opening and in physical contact with the dielectric layer, a conductive material filling the remaining part of the opening, and an interlayer between and adjoining the metallic barrier layer and the conductive material. The interlayer is preferably a metal compound layer.

摘要翻译： 提供了具有改进的电阻率的集成电路结构及其形成方法。 集成电路结构包括电介质层，电介质层中的开口和开口中的镶嵌结构。 镶嵌结构包括开口中的金属阻挡层和与电介质层物理接触的金属阻挡层，填充开口的剩余部分的导电材料以及金属阻挡层和导电材料之间的中间层。 中间层优选为金属化合物层。

公开(公告)号：US20080012133A1

公开(公告)日：2008-01-17

申请号：US11486893

申请日：2006-07-13

申请人： Chih-Chao Shih ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

发明人： Chih-Chao Shih ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC分类号： H01L23/52

CPC分类号： H01L23/53238 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76856 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, and a damascene structure in the opening. The damascene structure includes a metallic barrier layer in the opening and in physical contact with the dielectric layer, a conductive material filling the remaining part of the opening, and an interlayer between and adjoining the metallic barrier layer and the conductive material. The interlayer is preferably a metal compound layer.

摘要翻译： 提供了具有改进的电阻率的集成电路结构及其形成方法。 集成电路结构包括电介质层，电介质层中的开口和开口中的镶嵌结构。 镶嵌结构包括开口中的金属阻挡层和与电介质层物理接触的金属阻挡层，填充开口的剩余部分的导电材料以及金属阻挡层和导电材料之间的中间层。 中间层优选为金属化合物层。

公开(公告)号：US20060068604A1

公开(公告)日：2006-03-30

申请号：US10955519

申请日：2004-09-30

申请人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

发明人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76826 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A barrier layer and a fabrication thereof are disclosed. The barrier layer comprises at least one barrier material selected from the group consisting of Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr and Mo and at least one component of oxygen, nitrogen or carbon. A ratio of the component to the barrier material is not less than about 0.45. The fabrication method of the barrier layer applies a working pressure for forming the barrier layer from about 0.5 mTorr to about 200 mTorr substantially without forming crystalline material therein.

摘要翻译： 公开了阻挡层及其制造。 阻挡层包含选自Ta，W，Ti，Ru，Zr，Hf，V，Nb，Cr和Mo中的至少一种阻挡材料和氧，氮或碳的至少一种成分。 组分与阻隔材料的比例不小于约0.45。 阻挡层的制造方法施加用于形成阻挡层的工作压力，大约0.5mTorr至大约200mTorr，基本上不形成结晶材料。

公开(公告)号：US20090047780A1

公开(公告)日：2009-02-19

申请号：US12287516

申请日：2008-10-10

申请人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

发明人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

IPC分类号： H01L21/44

CPC分类号： H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

摘要： Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.

摘要翻译： 提供了一种形成复合阻挡层的方法，该复合阻挡层具有优异的阻挡性能，并且当复合阻挡层贯穿整个半导体器件时，两种电介质材料和导电材料具有优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常与电介质材料形成边界，并且结晶层通常与诸如互连材料的导电材料形成边界。

公开(公告)号：US08034709B2

公开(公告)日：2011-10-11

申请号：US12287516

申请日：2008-10-10

申请人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

发明人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

摘要： Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.

摘要翻译： 提供了一种形成复合阻挡层的方法，该复合阻挡层具有优异的阻挡性能，并且当复合阻挡层贯穿整个半导体器件时，两种介电材料和导电材料具有优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常与电介质材料形成边界，并且结晶层通常与诸如互连材料的导电材料形成边界。

公开(公告)号：US07453149B2

公开(公告)日：2008-11-18

申请号：US11024916

申请日：2004-12-28

申请人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

发明人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

IPC分类号： H01L23/48

CPC分类号： H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

摘要： A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.

摘要翻译： 当复合阻挡层延伸穿过整个半导体器件时，复合阻挡层为介电材料和导电材料提供优异的阻挡质量和优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常设置成与电介质材料形成边界，并且通常设置结晶层以与诸如互连材料的导电材料形成边界。

公开(公告)号：US20060027925A1

公开(公告)日：2006-02-09

申请号：US11024916

申请日：2004-12-28

申请人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

发明人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

IPC分类号： H01L29/788

CPC分类号： H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

摘要： A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.

摘要翻译： 当复合阻挡层延伸穿过整个半导体器件时，复合阻挡层为介电材料和导电材料提供优异的阻挡质量和优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常设置成与电介质材料形成边界，并且通常设置结晶层以与诸如互连材料的导电材料形成边界。

公开(公告)号：US20090258487A1

公开(公告)日：2009-10-15

申请号：US12102695

申请日：2008-04-14

申请人： Keng-Chu Lin ,  Chia-Cheng Chou ,  Chung-Chi Ko ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Shwang-Ming Jeng

发明人： Keng-Chu Lin ,  Chia-Cheng Chou ,  Chung-Chi Ko ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Shwang-Ming Jeng

IPC分类号： H01L21/4763

CPC分类号： H01L21/76825 ,  H01L21/3105

摘要： A method for forming an integrated circuit structure includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; generating hydrogen radicals using a remote plasma method; performing a first hydrogen radical treatment to the low-k dielectric layer using the hydrogen radicals; forming an opening in the low-k dielectric layer; filling the opening with a conductive material; and performing a planarization to remove excess conductive material on the low-k dielectric layer.

摘要翻译： 一种用于形成集成电路结构的方法包括提供半导体衬底; 在半导体衬底上形成低k电介质层; 使用远程等离子体法产生氢自由基; 使用氢自由基对低k电介质层进行第一次氢自由基处理; 在低k电介质层中形成开口; 用导电材料填充开口; 并执行平面化以去除低k电介质层上的过量导电材料。

公开(公告)号：US20090209098A1

公开(公告)日：2009-08-20

申请号：US12031280

申请日：2008-02-14

申请人： Li-Lin Su ,  Shing-Chyang Pan ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

发明人： Li-Lin Su ,  Shing-Chyang Pan ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873

摘要： A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form a seed layer in a first chamber; and performing a first etch step to remove a portion of the seed layer. The method may further include performing a second deposition step to increase the thickness of the seed layer. At least one of the first etch step and the second deposition step is performed in a second chamber different from the first chamber.

摘要翻译： 形成集成电路结构的方法包括形成电介质层; 在介电层中形成开口; 执行第一沉积步骤以在第一室中形成种子层; 以及执行第一蚀刻步骤以去除种子层的一部分。 该方法还可以包括执行第二沉积步骤以增加种子层的厚度。 在与第一室不同的第二室中执行第一蚀刻步骤和第二沉积步骤中的至少一个。