公开(公告)号：US20050211665A1

公开(公告)日：2005-09-29

申请号：US10813789

申请日：2004-03-26

申请人： Wei Gao ,  Yoshi Ono ,  John Conley

发明人： Wei Gao ,  Yoshi Ono ,  John Conley

IPC分类号： G02B1/11 ,  B29C33/38 ,  B29D11/00 ,  B29L11/00 ,  G02B3/00

CPC分类号： G02B3/0012 ,  G02B3/0056

摘要： Methods of forming microlens structure are provided. A hard mask is formed overlying a transparent material. An opening is patterned into the hard mask. Both the patterned hard mask and the underlying transparent material are exposed to a wet etch that etches the hard mask and the transparent material. As the hard mask is etched the opening increases exposing more of the transparent material. Depending on the etch selectivity, a lens shape is formed with sloped sidewalls. The lens opening may be filled with lens material to form a lens.

摘要翻译： 提供了形成微透镜结构的方法。 形成覆盖透明材料的硬掩模。 将开口图案化成硬掩模。 图案化的硬掩模和下面的透明材料都暴露于蚀刻硬掩模和透明材料的湿蚀刻。 当硬掩模被蚀刻时，开口增加了暴露更多的透明材料。 根据蚀刻选择性，形成具有倾斜侧壁的透镜形状。 透镜开口可以被透镜材料填充以形成透镜。

公开(公告)号：US07678512B2

公开(公告)日：2010-03-16

申请号：US11657326

申请日：2007-01-24

申请人： Yoshi Ono ,  Bruce D. Ulrich ,  Wei Gao

发明人： Yoshi Ono ,  Bruce D. Ulrich ,  Wei Gao

IPC分类号： G03F1/00

CPC分类号： G03F7/0005 ,  G03F1/50

摘要： A method of fabricating a grayscale reticle includes preparing a quartz wafer substrate; depositing a layer of SRO on the top surface of the quartz substrate; patterning and etching the SRO to form an initial microlens pattern using step-over lithography; patterning and etching the SRO to form a recessed pattern in the SRO; depositing an opaque film on the SRO; patterning and etching the opaque film; depositing and planarizing a planarizing layer; cutting the quartz wafer into rectangular pieces sized to be smaller than a selected blank reticle; bonding the a piece a to selected reticle blank to form a grayscale reticle; and using the grayscale reticle to form a microlens array on a photoimager.

摘要翻译： 制造灰度标线的方法包括制备石英晶片衬底; 在石英衬底的顶表面上沉积SRO层; 图案化和蚀刻SRO以使用逐步光刻形成初始微透镜图案; 图案化和蚀刻SRO以在SRO中形成凹陷图案; 在SRO上沉积不透明膜; 图案化和蚀刻不透明膜; 沉积和平坦化平坦化层; 将石英晶片切割成尺寸小于所选空白掩模版的矩形块; 将片a粘合到所选的掩模版坯料上以形成灰度标线; 并使用灰度标线在光学成像仪上形成微透镜阵列。

公开(公告)号：US07473640B2

公开(公告)日：2009-01-06

申请号：US10784662

申请日：2004-02-23

申请人： John F. Conley, Jr. ,  Yoshi Ono ,  Wei Gao

发明人： John F. Conley, Jr. ,  Yoshi Ono ,  Wei Gao

IPC分类号： H01L29/72

CPC分类号： H01L21/28079 ,  H01L21/823842 ,  H01L29/4958

摘要： A method, and corresponding transistor structure are provided for protecting the gate electrode from an underlying gate insulator. The method comprises: forming a gate insulator overlying a channel region; forming a first metal barrier overlying the gate insulator, having a thickness of less than 5 nanometers (nm); forming a second metal gate electrode overlying the first metal barrier, having a thickness of greater than 10 nm; and, establishing a gate electrode work function exclusively responsive to the second metal. The second metal gate electrode can be one of the following materials: elementary metals such as p+ poly, n+ poly. Ta, W, Re, RuO2, Pt, Ti, Hf, Zr, Cu, V, Ir, Ni, Mn, Co, NbO, Pd, Mo, TaSiN, and Nb, and binary metals such as WN, TaN, and TiN. The first metal barrier can be a binary metal, such as TaN, TiN, or WN.

摘要翻译： 提供了一种方法和相应的晶体管结构，用于保护栅极免受下层栅极绝缘体的影响。 该方法包括：形成覆盖沟道区的栅极绝缘体; 形成覆盖栅极绝缘体的厚度小于5纳米（nm）的第一金属屏障; 形成覆盖所述第一金属屏障的第二金属栅电极，其厚度大于10nm; 并且建立专门响应于第二金属的栅电极功函数。 第二金属栅电极可以是以下材料之一：元素金属，例如p + poly，n + poly。 Ta，W，Re，RuO 2，Pt，Ti，Hf，Zr，Cu，V，Ir，Ni，Mn，Co，NbO，Pd，Mo，TaSiN和Nb，二元金属如WN，TaN和TiN 。 第一金属屏障可以是二元金属，例如TaN，TiN或WN。

公开(公告)号：US20080197107A1

公开(公告)日：2008-08-21

申请号：US11709008

申请日：2007-02-20

申请人： Wei Gao ,  Bruce D. Ulrich ,  Yoshi Ono

发明人： Wei Gao ,  Bruce D. Ulrich ,  Yoshi Ono

IPC分类号： C25F3/00

CPC分类号： G03F1/68 ,  G03F1/50 ,  G03F1/54

摘要： A method of fabricating a grayscale mask includes preparing a quartz wafer; depositing a layer of Si3N4 on the quartz wafer; depositing a layer of titanium/TEOS directly on the Si3N4 layer on the backside of the quartz wafer; removing the layer of Si3N4 from the front side of the quartz wafer; depositing a layer of SRO directly on the front side of the quartz wafer; patterning a microlens array on the SRO layer; etching the SRO layer to form a microlens array in the SRO layer; depositing a layer of titanium; patterning and etching the titanium layer; depositing a layer of SiOxNy on the SRO microlens array; CMP to planarize the layer of SiOxNy removing the titanium/TEOS layer from the backside of the quartz wafer; bonding the planarized SiOxNy to a quartz reticle plate; and etching to remove Si3N4 from the bonded structure to form a grayscale mask reticle.

摘要翻译： 制造灰度掩模的方法包括制备石英晶片; 在石英晶片上沉积一层Si 3 N 4 N 4; 在石英晶片的背面上的Si 3 N 4 N 4层上直接沉积钛/ TEOS层; 从石英晶片的正面去除Si 3 N 4 N 4层; 在石英晶片的正面上直接沉积SRO层; 在SRO层上构图微透镜阵列; 蚀刻SRO层以在SRO层中形成微透镜阵列; 沉积一层钛; 图案化和蚀刻钛层; 在SRO微透镜阵列上沉积一层SiO 2 x N y O; CMP以平坦化从石英晶片的背面去除钛/ TEOS层的SiO 2 x N y层; 将平坦化的SiO x N N y N键合到石英光罩板上; 以及蚀刻以从结合结构去除Si 3 N 4 N 4以形成灰度掩模掩模版。

公开(公告)号：US20080176148A1

公开(公告)日：2008-07-24

申请号：US11657326

申请日：2007-01-24

申请人： Yoshi Ono ,  Bruce D. Ulrich ,  Wei Gao

发明人： Yoshi Ono ,  Bruce D. Ulrich ,  Wei Gao

IPC分类号： G03F1/00

CPC分类号： G03F7/0005 ,  G03F1/50

摘要： A method of fabricating a grayscale reticle includes preparing a quartz wafer substrate; depositing a layer of SRO on the top surface of the quartz substrate; patterning and etching the SRO to form an initial microlens pattern using step-over lithography; patterning and etching the SRO to form a recessed pattern in the SRO; depositing an opaque film on the SRO; patterning and etching the opaque film; depositing and planarizing a planarizing layer; cutting the quartz wafer into rectangular pieces sized to be smaller than a selected blank reticle; bonding the a piece a to selected reticle blank to form a grayscale reticle; and using the grayscale reticle to form a microlens array on a photoimager.

摘要翻译： 制造灰度标线的方法包括制备石英晶片衬底; 在石英衬底的顶表面上沉积SRO层; 图案化和蚀刻SRO以使用逐步光刻形成初始微透镜图案; 图案化和蚀刻SRO以在SRO中形成凹陷图案; 在SRO上沉积不透明膜; 图案化和蚀刻不透明膜; 沉积和平坦化平坦化层; 将石英晶片切割成尺寸小于所选空白掩模版的矩形块; 将片a粘合到所选的掩模版坯料上以形成灰度标线; 并使用灰度标线在光学成像仪上形成微透镜阵列。

公开(公告)号：US20080164569A1

公开(公告)日：2008-07-10

申请号：US11582275

申请日：2006-10-16

申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L29/00

CPC分类号： H01L27/15 ,  H01L33/0004 ,  H01L33/343

摘要： A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.

摘要翻译： 一种制造电致发光器件的方法包括：在制备的衬底上，在作为发光层的栅极氧化物层上沉积稀土掺杂的富硅层; 并对该结构进行退火和氧化以修复对稀土掺杂的富硅层造成的任何损伤; 并将电致发光器件并入CMOS IC。 根据本发明的方法制造的电致发光器件包括：衬底，形成在栅极氧化物层上的用于发射预定波长的光的稀土掺杂富硅层; 在稀土掺杂的富硅层上形成的顶部电极; 并在其附近制造相关的CMOS IC结构。

公开(公告)号：US20060172555A1

公开(公告)日：2006-08-03

申请号：US11049594

申请日：2005-02-01

申请人： Wei Gao ,  Tingkai Li ,  Yoshi Ono ,  Sheng Hsu

发明人： Wei Gao ,  Tingkai Li ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L21/31

CPC分类号： C23C14/5806 ,  C23C14/10

摘要： A method of forming a silicon-rich silicon oxide layer having nanometer sized silicon particles therein includes preparing a substrate; preparing a target; placing the substrate and the target in a sputtering chamber; setting the sputtering chamber parameters; depositing material from the target onto the substrate to form a silicon-rich silicon oxide layer; and annealing the substrate to form nanometer sized silicon particles therein.

摘要翻译： 形成其中具有纳米尺寸硅颗粒的富硅氧化硅层的方法包括制备衬底; 准备一个目标 将基板和靶放置在溅射室中; 设置溅射室参数; 将材料从靶材沉积到衬底上以形成富硅氧化硅层; 并对衬底退火以在其中形成纳米尺寸的硅颗粒。

公开(公告)号：US07887980B2

公开(公告)日：2011-02-15

申请号：US12193568

申请日：2008-08-18

申请人： Bruce D. Ulrich ,  Yoshi Ono ,  Wei Gao

发明人： Bruce D. Ulrich ,  Yoshi Ono ,  Wei Gao

IPC分类号： G03F1/00 ,  G03F7/00

CPC分类号： G03F1/50 ,  G03F7/0005

摘要： A sub-resolutional grayscale reticle and associated fabrication method have been presented. The method provides a transparent substrate, and forms a plurality of coincident partial-light transmissive layers overlying the transparent substrate. A pattern is formed, sub-resolutional at a first wavelength, in at least one of the transmissive layers. If there are n transmissive layers, the reticle transmits at least (n+1) intensities of light. In one aspect, each of the plurality of transmissive layers has the same extinction coefficient and the same thickness. In other aspects, the transmissive layers may have different thickness. Then, even if the extinction coefficients are the same, the attenuation of light through each layer is different. The transmission characteristics of the reticle can be further varied if the transmissive layers have different extinction coefficients. Likewise, the transmission characteristics through the sub-resolutional patterns can be varied.

摘要翻译： 已经提出了一种亚分辨灰度标线和相关的制造方法。 该方法提供透明基板，并且形成覆盖透明基板的多个重合部分透光层。 在至少一个透射层中形成在第一波长处副溶液的图案。 如果存在n个透射层，则光罩传播至少（n + 1）个光强。 在一个方面，多个透射层中的每一个具有相同的消光系数和相同的厚度。 在其它方面，透射层可以具有不同的厚度。 那么即使消光系数相同，每层的光的衰减也是不同的。 如果透射层具有不同的消光系数，则可以进一步改变掩模版的透射特性。 同样，可以改变通过子解决图案的传输特性。

公开(公告)号：US07838174B2

公开(公告)日：2010-11-23

申请号：US11657258

申请日：2007-01-24

申请人： Wei Gao ,  Bruce D. Ulrich ,  Yoshi Ono ,  Steven R. Droes

发明人： Wei Gao ,  Bruce D. Ulrich ,  Yoshi Ono ,  Steven R. Droes

IPC分类号： G03F1/00 ,  G03C5/00

CPC分类号： G03F1/50 ,  H01L27/14685

摘要： A method of fabricating a grayscale mask includes preparing a silicon wafer; depositing a layer of Si3N4 directly on the silicon wafer; implanting H+ ions into the silicon wafer to form a defect layer; depositing a first layer of SiOxNy directly on the Si3N4 layer; depositing a layer of SRO directly on the first layer of SiOxNy; patterning and etching the SRO layer to form a microlens array in the SRO layer; depositing a second layer of SiOxNy on the SRO microlens array; CMP to planarize the second layer of SiOxNy; bonding and cleaving the planarized SiOxNyto a quartz plate to form a graymask reticle; etching to remove silicon from the bonded structure; etching to remove SiOxNy and Si3N4 from the bonded structure; and cleaning and drying the graymask reticle.

摘要翻译： 制造灰度掩模的方法包括制备硅晶片; 在硅晶片上直接沉积一层Si3N4; 将H +离子注入到硅晶片中以形成缺陷层; 在Si 3 N 4层上直接沉积第一层SiOxNy层; 在第一层SiOxNy上直接沉积一层SRO; 图案化和蚀刻SRO层以在SRO层中形成微透镜阵列; 在SRO微透镜阵列上沉积第二层SiOxNy; CMP平面化第二层SiOxNy; 将平面化的SiO x N y键合并切割成石英板以形成灰色掩模掩模; 蚀刻以从结合结构去除硅; 蚀刻从结合结构去除SiOxNy和Si3N4; 并清理并干燥灰色掩模。

公开(公告)号：US07589464B2

公开(公告)日：2009-09-15

申请号：US11070051

申请日：2005-03-01

申请人： John F. Conley, Jr. ,  David R. Evans ,  Wei Gao ,  Yoshi Ono

发明人： John F. Conley, Jr. ,  David R. Evans ,  Wei Gao ,  Yoshi Ono

IPC分类号： H05B33/26

CPC分类号： H05B33/10 ,  B82Y20/00 ,  C09K11/54 ,  C09K11/642 ,  H01L33/18 ,  H05B33/14

摘要： A device and a fabrication method are provided for an EL device with a nanotip-contoured phosphor layer. The method comprises: forming a bottom electrode with nanotips; forming a phosphor layer overlying the bottom electrode, having irregularly-shaped top and bottom surfaces; and, forming a top electrode overlying the phosphor layer. The bottom electrode top surface has a nanotip contour, and the phosphor layer irregularly-shaped top and bottom surfaces have contours approximately matching the bottom electrode top surface nanotip contour. In one aspect, a contoured bottom dielectric is interposed between the bottom electrode and the phosphor layer, having top and bottoms surfaces with contours approximately matching the nanotip contour. Likewise, a top dielectric may be interposed between the top electrode and the phosphor layer, having a bottom surface with a contour approximately matching the contour of phosphor layer top surface.

摘要翻译： 提供了一种具有纳米尺度荧光体层的EL器件的器件和制造方法。 该方法包括：形成具有纳米尖端的底部电极; 形成覆盖在底部电极上的荧光体层，具有不规则形状的顶部和底部表面; 并且形成覆盖磷光体层的顶部电极。 底部电极顶表面具有纳米尖端轮廓，并且荧光体层不规则形状的顶表面和底表面具有与底部电极顶表面纳米尖端轮廓近似匹配的轮廓。 在一个方面，在底部电极和荧光体层之间插入有轮廓的底部电介质，其具有顶部和底部表面，轮廓几乎与纳米尖端轮廓相匹配。 类似地，顶部电介质可以插入在顶部电极和荧光体层之间，具有大致与荧光体层顶表面的轮廓相匹配的轮廓的底面。