公开(公告)号：US20070091715A1

公开(公告)日：2007-04-26

申请号：US11340471

申请日：2006-01-27

申请人： Kota Hara ,  Akira Kikutake

发明人： Kota Hara ,  Akira Kikutake

IPC分类号： G11C8/00

CPC分类号： G11C7/1027 ,  G11C11/4076 ,  G11C2207/002

摘要： An internal address generating circuit sequentially generates internal addresses in the burst read operation, with an external address being set as an initial value. A memory core has plural memory cells and sequentially outputs, in response to activation of a column selection signal, data read from the memory cells corresponding to the internal addresses in the burst read operation. In the burst read operation, a column control circuit in a memory core control circuit repeats activation of the column selection signal for a certain period during an activation period of an external control signal and forcibly deactivates the column selection signal in synchronization with deactivation of the external control signal. In the burst read operation, an operation state control circuit in the memory core control circuit deactivates an operation state control signal after a predetermined time has elapsed from the deactivation of the external control signal.

摘要翻译： 内部地址产生电路在外部地址被设置为初始值的情况下顺序地生成突发读取操作中的内部地址。 存储器核具有多个存储单元，并且响应于列选择信号的激活顺序地输出从与突发读操作中的内部地址对应的存储单元读出的数据。 在突发读取操作中，存储器核心控制电路中的列控制电路在外部控制信号的激活周期期间重复列选择信号的激活一段时间，并且与停止外部控制信号同步地强制停止列选择信号 控制信号。 在突发读取操作中，存储器核心控制电路中的操作状态控制电路在从外部控制信号的去激活经过预定时间之后，使操作状态控制信号无效。

公开(公告)号：US07180822B2

公开(公告)日：2007-02-20

申请号：US10994632

申请日：2004-11-23

申请人： Kota Hara ,  Shinichi Yamada

发明人： Kota Hara ,  Shinichi Yamada

IPC分类号： G11C8/00

CPC分类号： G11C11/406 ,  G11C7/1027 ,  G11C7/20 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/4072

摘要： A semiconductor memory device, in which a burst operation is performed using a memory core, has a read/write trigger signal generating circuit and a read/write signal generating circuit. The read/write trigger signal generating circuit generates a read/write signal request from a predetermined timing signal during the burst operation. The read/write signal generating circuit receives an output signal from the read/write trigger signal generating circuit and outputs a read/write signal after a core operation just prior to receipt of the output signal is complete and the subsequent activation of a row side is complete.

摘要翻译： 使用存储器核进行突发操作的半导体存储器件具有读/写触发信号生成电路和读/写信号生成电路。 读/写触发信号产生电路在脉冲串操作期间从预定定时信号产生读/写信号请求。 读/写信号发生电路在读/写触发信号产生电路接收输出信号，并且在接收到输出信号完成之后在核心操作之后输出读/写信号，并且随后的行侧激活 完成。

公开(公告)号：US07032142B2

公开(公告)日：2006-04-18

申请号：US10271533

申请日：2002-10-17

申请人： Shinya Fujioka ,  Waichiro Fujieda ,  Kota Hara ,  Toru Koga ,  Katsuhiro Mori

发明人： Shinya Fujioka ,  Waichiro Fujieda ,  Kota Hara ,  Toru Koga ,  Katsuhiro Mori

IPC分类号： G11C29/00 ,  G11C7/00 ,  G06F11/00

CPC分类号： G11C29/42 ,  G06F11/106 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C2211/4062

摘要： A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.

公开(公告)号：US20060068229A1

公开(公告)日：2006-03-30

申请号：US11234083

申请日：2005-09-26

申请人： Kota Hara ,  Koichi Shimokawa ,  Kota Suzuki

发明人： Kota Hara ,  Koichi Shimokawa ,  Kota Suzuki

IPC分类号： G11B5/65

CPC分类号： C10M177/00 ,  C10M107/38 ,  C10M131/10 ,  C10M2213/04 ,  C10M2213/043 ,  C10N2230/42 ,  C10N2240/204 ,  C10N2250/121 ,  C10N2270/00 ,  G11B5/725 ,  G11B5/8408

摘要： On producing a lubricant which is used in making a lubrication layer included in a magnetic disk from the lubricant, a phosphorus-containing compound is removed from a raw-material lubricant including the phosphorus-containing compound to produce the lubricant. The magnetic disk includes a substrate on which at least a magnetic layer, a protection layer, and the lubrication layer formed by the use of the lubricant are successively formed.

公开(公告)号：US20050170136A1

公开(公告)日：2005-08-04

申请号：US11097283

申请日：2005-04-04

申请人： Koichi Shimokawa ,  Kota Hara

发明人： Koichi Shimokawa ,  Kota Hara

IPC分类号： G11B5/725 ,  G11B5/84 ,  B32B3/02 ,  B32B1/00

CPC分类号： G11B5/725 ,  G11B5/8408

摘要： A magnetic recording disk having a substrate, a magnetic layer formed on the substrate, a protective layer formed on the magnetic layer and a lubricant layer formed on the protective layer, the lubricant layer containing a perfluoropolyether compound having an end moiety containing a phosphazene ring and a perfluoropolyether compound having an end moiety containing a hydroxyl group, or the lubricant layer containing a perfluoropolyether compound having an end moiety containing a hydroxyl group on the protective layer side and a perfluoropolyether compound having an end moiety containing a phosphazene ring on the other surface side, and a process for manufacturing each of these magnetic recording disks.

摘要翻译： 一种磁记录盘，其具有基板，形成在基板上的磁性层，形成在磁性层上的保护层和形成在保护层上的润滑层，润滑层含有具有含有磷腈环的末端部分的全氟聚醚化合物和 具有包含羟基的末端部分的全氟聚醚化合物，或含有在保护层侧具有羟基的末端部分的全氟聚醚化合物的润滑剂层和在另一个表面侧具有含有磷腈环的末端部分的全氟聚醚化合物 ，以及这些磁记录盘的制造方法。

公开(公告)号：US06614712B2

公开(公告)日：2003-09-02

申请号：US10329669

申请日：2002-12-27

申请人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

发明人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

IPC分类号： G11C800

CPC分类号： G11C8/08 ,  G11C5/06

摘要： A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.