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    Memory circuit having compressed testing function
    3.
    发明授权
    Memory circuit having compressed testing function 有权
    存储电路具有压缩测试功能

    公开(公告)号：US06731553B2

    公开(公告)日：2004-05-04

    申请号：US10270196

    申请日：2002-10-15

    申请人： Shinya Fujioka ,  Waichiro Fujieda ,  Kota Hara

    发明人： Shinya Fujioka ,  Waichiro Fujieda ,  Kota Hara

    IPC分类号： G11C700

    CPC分类号： G11C29/40

    摘要： A multi-bit output configuration memory circuit comprises: a memory core having a normal cell array and a redundant cell array, which have a plurality of memory cells; N output terminals which respectively output N-bit output read out from the memory core; an output circuit provided between the output terminals and the memory core, which detects whether each L-bit output of the N-bit output (N=L×M) read out from said memory core matches or not and outputs a compressed output which becomes the output data in the event of a match while becomes a third state in the event of a non-match, to a first output terminal of the N output terminals. Responding to each of a plurality of test commands or the test control signals of the external terminals, the compressed output of the M groups of L-bit output is outputted in time shared.

    摘要翻译： 多比特输出配置存储器电路包括：具有正常单元阵列的存储器核心和具有多个存储单元的冗余单元阵列; N个输出端子，分别输出从存储器芯读出的N位输出; 输出电路，设置在输出端子和存储器核心之间，其检测从所述存储器芯片读出的N位输出（N = L×M）的每个L位输出是否匹配，并输出成为输出的压缩输出 在匹配的情况下的数据在不匹配的情况下变为第三状态时，输出到N个输出端的第一输出端。 响应多个测试命令或外部终端的测试控制信号中的每一个，M个组的L位输出的压缩输出以时间共享的形式被输出。

    Semiconductor memory
    4.
    发明授权
    Semiconductor memory 有权

    公开(公告)号：US06621750B2

    公开(公告)日：2003-09-16

    申请号：US10155029

    申请日：2002-05-28

    申请人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

    发明人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

    IPC分类号： G11C700

    CPC分类号： G11C29/808 ,  G11C29/812 ,  G11C29/848

    摘要： A redundancy memory circuit stores a defect address indicating a defective memory cell row. A redundancy control circuit disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables a redundancy memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables redundancy memory cell rows instead of these memory cell rows. Consequently, not only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. Thus, the redundancy memory circuit can be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. As a result, the semiconductor memory can be reduced in chip size.

    Semiconductor integrated circuit
    5.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06683491B2

    公开(公告)日：2004-01-27

    申请号：US10106107

    申请日：2002-03-27

    申请人： Toru Koga ,  Shinya Fujioka ,  Katsuhiro Mori

    发明人： Toru Koga ,  Shinya Fujioka ,  Katsuhiro Mori

    IPC分类号： G05F110

    CPC分类号： G11C11/4074 ,  G11C2207/2227

    摘要： First and second voltage generators generate a first internal power supply voltage to be supplied to a first internal power supply line and a second internal power supply voltage to be supplied to a second internal power supply line, respectively. A short circuit shorts the first and second internal power supply lines when operations of both the first and second voltage generators are suspended. The first and second internal power supply lines become floating, and charges stored in the respective internal power supply lines drain out gradually. Here, since the charges are redistributed to both of the internal power supply lines, the first and second internal power supply voltages become equal in value as they drop off. Consequently, the first and second internal power supply voltages can be prevented from inversion, and internal circuits connected to both the first and second internal power supply lines can be precluded from malfunctioning.

    摘要翻译： 第一和第二电压发生器产生分别提供给第一内部电源线和第二内部电源电压的第一内部电源电压以供给第二内部电源线。 当第一和第二电压发生器的操作被暂停时，短路使第一和第二内部电源线短路。 第一和第二内部电源线变为浮动，并且各个内部电源线中存储的电荷逐渐排出。 这里，由于电荷被重新分配给两个内部电源线，所以第一和第二内部电源电压随着它们的下降而变得相等。 因此，可以防止第一和第二内部电源电压反转，并且可以防止连接到第一和第二内部电源线的内部电路发生故障。

    Semiconductor memory and method of operating same
    6.
    发明授权
    Semiconductor memory and method of operating same 有权

    公开(公告)号：US06477093B2

    公开(公告)日：2002-11-05

    申请号：US09901628

    申请日：2001-07-11

    申请人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Waichiro Fujieda

    发明人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Waichiro Fujieda

    IPC分类号： G11C800

    CPC分类号： G11C8/06 ,  G11C8/00

    摘要： An address signal is transmited to a decoder before the activation of a control signal operating a memory cell. Here, the decoder is inactivated. Subsequently, after the activation of the control signal, the reception of a new address signal is inhibited, and the decoder is activated at the same time. Therefore, the decoder starts operating at an earlier timing of the operating cycle, outputting a decoding signal. This means reduction in access time. Moreover, the reception of a new address signal is inhibited after the activation of the control signal. This prevents the decoder from decoding incorrect address signals ascribable to noises and the like, thereby avoiding malfunctions.

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06545924B2

    公开(公告)日：2003-04-08

    申请号：US09929357

    申请日：2001-08-15

    申请人： Waichiro Fujieda ,  Shinya Fujioka

    发明人： Waichiro Fujieda ,  Shinya Fujioka

    IPC分类号： G11C700

    CPC分类号： G11C11/406

    摘要： A semiconductor memory device having a self-refresh function includes a detection circuit detecting a change of an output enable signal and generating a state transition detection signal, and a decision circuit comparing the state transition detection signal and a refresh request signal internally generated and generating a signal that indicates a corresponding circuit operation.

    Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations
    8.
    发明授权
    Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations 有权
    半导体存储器件与时钟信号同步工作，用于高速数据写入和数据读取操作

    公开(公告)号：US06427197B1

    公开(公告)日：2002-07-30

    申请号：US09394891

    申请日：1999-09-13

    申请人： Yasuharu Sato ,  Tadao Aikawa ,  Shinya Fujioka ,  Waichiro Fujieda ,  Hitoshi Ikeda ,  Hiroyuki Kobayashi

    发明人： Yasuharu Sato ,  Tadao Aikawa ,  Shinya Fujioka ,  Waichiro Fujieda ,  Hitoshi Ikeda ,  Hiroyuki Kobayashi

    IPC分类号： G11C800

    CPC分类号： G11C7/1072 ,  G11C7/1039

    摘要： The present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted. According to the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length. When writing successively or reading successively, moreover, the command cycle can made short irrespective of the burst length.

    摘要翻译： 本发明是一种存储电路，用于响应于写命令，写入根据突发长度确定的指定数量的写入数据，包括：第一级，用于与第一级同时输入，然后保持行地址和列地址 写命令 第二级具有经由流水线开关连接到第一级的存储器核，其中行地址和列地址被解码，字线和检测放大器被激活; 用于串行输入写入数据并且将写入数据并行地发送到存储器核心的第三级; 以及串行数据检测电路，用于在输入了规定数量的写入数据之后，产生用于使流水线开关导通的写入流水线控制信号。 根据本发明，在呈现流水线结构的FCRAM中，可以在以突发长度安全地取出写入数据之后激活第二级中的存储器核心。 此外，当连续写入或连续读取时，无论突发长度如何，命令循环可以变短。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06529439B2

    公开(公告)日：2003-03-04

    申请号：US09789514

    申请日：2001-02-22

    申请人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    发明人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    IPC分类号： G11C800

    CPC分类号： G11C8/08 ,  G11C5/06

    摘要： A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06614712B2

    公开(公告)日：2003-09-02

    申请号：US10329669

    申请日：2002-12-27

    申请人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    发明人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    IPC分类号： G11C800

    CPC分类号： G11C8/08 ,  G11C5/06

    摘要： A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.