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公开(公告)号：US09099177B2
公开(公告)日：2015-08-04
申请号：US14124725
申请日：2011-06-10
CPC分类号： G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/71 , G11C2213/75 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.
摘要翻译： 为了提供适合于小型化并允许接触电阻降低的半导体存储器件，存储器阵列（MA）的布线结构如下形成。 也就是说，字线（2）和位线（3）彼此并行扩展，每条字线与另一个字线捆绑，每个位线与另一个位线捆绑，并且两个位线 在相应的捆绑的两条字线上垂直形成的电路分离。 这样的配置使得可以：在电线的捆扎部分（MLC）处形成较大的接触; 并降低适于小型化的存储器阵列中的接触电阻。
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公开(公告)号：US20140218999A1
公开(公告)日：2014-08-07
申请号：US14124725
申请日：2011-06-10
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/71 , G11C2213/75 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.
摘要翻译： 为了提供适合于小型化并允许接触电阻降低的半导体存储器件，存储器阵列（MA）的布线结构如下形成。 也就是说，字线（2）和位线（3）彼此并行扩展，每条字线与另一个字线捆绑，每个位线与另一个位线捆绑，并且两个位线 在相应的捆绑的两条字线上垂直形成的电路分离。 这样的配置使得可以：在电线的捆扎部分（MLC）处形成更大的接触; 并降低适于小型化的存储器阵列中的接触电阻。
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公开(公告)号：US08592789B2
公开(公告)日：2013-11-26
申请号：US13109985
申请日：2011-05-17
IPC分类号： H01L45/00
CPC分类号： H01L27/2481 , H01L27/1021 , H01L27/2409 , H01L27/2436 , H01L27/2472
摘要： In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.
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公开(公告)号：US08730717B2
公开(公告)日：2014-05-20
申请号：US13104005
申请日：2011-05-09
申请人： Satoru Hanzawa , Yoshitaka Sasago
发明人： Satoru Hanzawa , Yoshitaka Sasago
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/71 , G11C2213/72 , G11C2213/75 , G11C2213/78 , H01L27/2454 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/124 , H01L45/144
摘要： A semiconductor device has multiple memory cell groups arranged at intersections between multiple word lines and multiple bit lines intersecting the word lines. The memory cell groups each have first and second memory cells connected in series. Each of the first and the second memory cells has a select transistor and a resistive storage device connected in parallel. The gate electrode of the select transistor in the first memory cell is connected with a first gate line, and the gate electrode of the select transistor in the second memory cell is connected to a second gate line. A first circuit block for driving the word lines (word driver group WDBK) is arranged between a second circuit block for driving the first and second gate lines (phase-change-type chain cell control circuit PCCCTL) and multiple memory cell groups (memory cell array MA).
摘要翻译： 半导体器件具有布置在多个字线和与字线相交的多个位线之间的交叉处的多个存储单元组。 存储单元组各自具有串联连接的第一和第二存储器单元。 第一和第二存储单元中的每一个具有并联连接的选择晶体管和电阻存储器件。 第一存储单元中的选择晶体管的栅电极与第一栅极线连接，第二存储单元中的选择晶体管的栅电极连接到第二栅极线。 用于驱动字线的第一电路块（字驱动器组WDBK）被布置在用于驱动第一和第二栅极线（相变型链单元控制电路PCCCTL）的第二电路块和多个存储单元组 阵列MA）。
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公开(公告)号：US08699262B2
公开(公告)日：2014-04-15
申请号：US13270299
申请日：2011-10-11
申请人： Takao Watanabe , Satoru Hanzawa , Yoshitaka Sasago
发明人： Takao Watanabe , Satoru Hanzawa , Yoshitaka Sasago
IPC分类号： G11C11/24
CPC分类号： H01L45/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/75 , G11C2213/78 , G11C2213/79 , H01L27/2481
摘要： Adverse effects of a parasitic resistance and a parasitic capacitance of a driver circuit to a memory cell causes problems of thermal disturbance to a not-selected cell, unevenness of application voltage, degradation of a memory element in reading. A capacitor (C) is provided above or beneath a memory cell (MC) that includes a memory element to which a current write memory information and a selection element connected to the memory element. A charge stored in this capacitor writes to the memory element.
摘要翻译： 驱动电路的寄生电阻和寄生电容对存储单元的不利影响引起对未选择单元的热扰动，施加电压的不均匀性，读取中存储元件的劣化的问题。 电容器（C）设置在存储单元（MC）的上方或下方，存储单元（MC）包括与存储元件连接的当前写入存储器信息和选择元件的存储元件。 存储在该电容器中的电荷写入存储器元件。
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公开(公告)号：US20120087178A1
公开(公告)日：2012-04-12
申请号：US13270299
申请日：2011-10-11
申请人： Takao WATANABE , Satoru Hanzawa , Yoshitaka Sasago
发明人： Takao WATANABE , Satoru Hanzawa , Yoshitaka Sasago
IPC分类号： G11C11/24
CPC分类号： H01L45/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/75 , G11C2213/78 , G11C2213/79 , H01L27/2481
摘要： Adverse effects of a parasitic resistance and a parasitic capacitance of a driver circuit to a memory cell causes problems of thermal disturbance to a not-selected cell, unevenness of application voltage, degradation of a memory element in reading. A capacitor (C) is provided above or beneath a memory cell (MC) that includes a memory element to which a current write memory information and a selection element connected to the memory element. A charge stored in this capacitor writes to the memory element.
摘要翻译： 驱动电路的寄生电阻和寄生电容对存储单元的不利影响引起对未选择单元的热扰动，施加电压的不均匀性，读取中存储元件的劣化的问题。 电容器（C）设置在存储单元（MC）的上方或下方，存储单元（MC）包括与存储元件连接的当前写入存储器信息和选择元件的存储元件。 存储在该电容器中的电荷写入存储器元件。
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公开(公告)号：US20140246646A1
公开(公告)日：2014-09-04
申请号：US14349386
申请日：2011-10-07
IPC分类号： H01L27/24
CPC分类号： H01L27/2481 , H01L27/2409 , H01L27/2454 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/144 , H01L45/1683
摘要： A memory cell array having such a structure that can be realized with a simpler process and ideal for realizing a higher density is provided. Memory cells have a structure in which channel layers (88p and 89p) are formed on the side surfaces of each of a plurality of stacked structures which extends in the Y direction and is periodically formed in the X direction with a gate insulator film layer (9) interposed, and a resistance-change material layer (7) is formed so as to be electrically connected to two adjacent channel layers of the channel layers. Due to such a structure, it is not necessary to perform such a very difficult step that processes the resistance-change material and the silicons collectively and it is possible to provide the memory cell array with a simpler process.
摘要翻译： 提供具有能够以更简单的处理实现并且实现更高密度的理想的具有这种结构的存储单元阵列。 存储单元具有这样的结构，其中沟道层（88p和89p）形成在多个层叠结构中的每一个在Y方向上延伸并且沿X方向周期性地形成的栅极绝缘膜层（9 ），并且形成电阻变化材料层（7），以电连接到沟道层的两个相邻沟道层。 由于这样的结构，不需要进行这样一个非常困难的步骤，即整体地处理电阻变化材料和硅，并且可以以更简单的工艺来提供存储单元阵列。
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公开(公告)号：US08604456B2
公开(公告)日：2013-12-10
申请号：US13366544
申请日：2012-02-06
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/1675 , Y10S438/90
摘要： Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.
摘要翻译： 本发明提供一种非易失性存储装置，其包括：配置有交叉点存储单元的相变存储器，其中由相变材料形成的存储元件和由二极管形成的选择元件组合。 存储单元配置有由相变材料形成的存储元件和由具有第一多晶硅膜，第二多晶硅膜和第三多晶硅膜的堆叠结构的二极管形成的选择元件。 存储单元布置在沿着第一方向延伸的多个第一金属布线的交点和沿着与第一方向正交的第二方向延伸的多个第三金属布线。 在相邻的选择元件之间和相邻的存储元件之间形成中间膜，并且在设置在相邻的存储元件之间的层间膜中形成空隙。
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公开(公告)号：US09293508B2
公开(公告)日：2016-03-22
申请号：US14349386
申请日：2011-10-07
CPC分类号： H01L27/2481 , H01L27/2409 , H01L27/2454 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/144 , H01L45/1683
摘要： A memory cell array having such a structure that can be realized with a simpler process and ideal for realizing a higher density is provided. Memory cells have a structure in which channel layers (88p and 89p) are formed on the side surfaces of each of a plurality of stacked structures which extends in the Y direction and is periodically formed in the X direction with a gate insulator film layer (9) interposed, and a resistance-change material layer (7) is formed so as to be electrically connected to two adjacent channel layers of the channel layers. Due to such a structure, it is not necessary to perform such a very difficult step that processes the resistance-change material and the silicons collectively and it is possible to provide the memory cell array with a simpler process.
摘要翻译： 提供具有能够以更简单的处理实现并且实现更高密度的理想的具有这种结构的存储单元阵列。 存储单元具有这样的结构，其中沟道层（88p和89p）形成在多个层叠结构中的每一个在Y方向上延伸并且沿X方向周期性地形成的栅极绝缘膜层（9 ），并且形成电阻变化材料层（7），以电连接到沟道层的两个相邻沟道层。 由于这样的结构，不需要进行这样一个非常困难的步骤，即整体地处理电阻变化材料和硅，并且可以以更简单的工艺来提供存储单元阵列。
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公开(公告)号：US20100032637A1
公开(公告)日：2010-02-11
申请号：US12434633
申请日：2009-05-02
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/1675 , Y10S438/90
摘要： Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.
摘要翻译： 本发明提供一种非易失性存储装置，其包括：配置有交叉点存储单元的相变存储器，其中由相变材料形成的存储元件和由二极管形成的选择元件组合。 存储单元配置有由相变材料形成的存储元件和由具有第一多晶硅膜，第二多晶硅膜和第三多晶硅膜的堆叠结构的二极管形成的选择元件。 存储单元布置在沿着第一方向延伸的多个第一金属布线的交点和沿着与第一方向正交的第二方向延伸的多个第三金属布线。 在相邻的选择元件之间和相邻的存储元件之间形成中间膜，并且在设置在相邻的存储元件之间的层间膜中形成空隙。
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