公开(公告)号：US07259089B2

公开(公告)日：2007-08-21

申请号：US11032015

申请日：2005-01-11

申请人： Ryuichi Kanamura

发明人： Ryuichi Kanamura

IPC分类号： H01L21/467

CPC分类号： H01L21/76811 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76813 ,  H01L21/76835

摘要： A semiconductor device manufacturing method includes the steps of: forming first and second insulation films on a substrate provided with a first wiring; sequentially forming first to third mask layers on the second insulation film; forming a wiring groove pattern in the third mask layer; selectively processing the third mask layer, formed to project into the inside of the wiring groove pattern, into a tapered shape; forming a contact hole pattern in the second and first mask layer, and removing the tapered shape portions of the third mask layer; and forming wiring grooves in the second insulation film by etching using the third mask layer, and forming contact holes in the insulation film by etching using the second and first mask layers.

摘要翻译： 半导体器件制造方法包括以下步骤：在设置有第一布线的基板上形成第一绝缘膜和第二绝缘膜; 在第二绝缘膜上依次形成第一至第三掩模层; 在所述第三掩模层中形成布线槽图案; 选择性地处理形成为突出到布线槽图案的内部的第三掩模层为锥形; 在所述第二掩模层和所述第一掩模层中形成接触孔图案，并且去除所述第三掩模层的锥形形状部分; 以及通过使用第三掩模层的蚀刻在第二绝缘膜中形成布线槽，并且通过使用第二和第一掩模层的蚀刻在绝缘膜中形成接触孔。

公开(公告)号：US20060055046A1

公开(公告)日：2006-03-16

申请号：US11268905

申请日：2005-11-08

申请人： Ryuichi Kanamura

发明人： Ryuichi Kanamura

IPC分类号： H01L23/52

CPC分类号： H01L21/76852 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The present invention provides a semiconductor device having a multilayer wiring structure including a lower Cu buried-wiring layer, a SiC film, a SiOC film of 400 nm in thickness functioning as an interlayer insulating film, and an upper Cu buried-wiring layer electrically connected to the lower buried-wiring layer through contact plugs passing through the interlayer insulating film. The contact plugs and the upper Cu buried wiring layer are formed a single burying step of the dual damascene process. The SiOC film has a carbon content of about 12 atomic % and a relative dielectric constant of about 3.0. The upper Cu buried wiring layer is formed by burying a Cu film, through a barrier metal, in wiring grooves which are provided in the inter-wiring insulating film including a laminated film of an organic film, e.g., a PAE film of 200 nm in thickness, and a SiOC film of 150 nm in thickness.

摘要翻译： 本发明提供一种半导体器件，其具有多层布线结构，该多层布线结构包括下部Cu掩埋布线层，SiC膜，作为层间绝缘膜的厚度为400nm的SiOC膜，以及电连接的上部Cu掩埋布线层 通过穿过层间绝缘膜的接触插塞到下埋入布线层。 接触插塞和上铜掩埋布线层形成双镶嵌工艺的单一掩埋步骤。 SiOC膜具有约12原子％的碳含量和约3.0的相对介电常数。 上部铜掩埋布线层通过在隔离金属中埋设Cu膜而形成，该布线槽设置在包括有机膜的层合膜的布线间绝缘膜中，例如200nm的PAE膜 厚度和厚度为150nm的SiOC膜。

公开(公告)号：US20050170636A1

公开(公告)日：2005-08-04

申请号：US11097137

申请日：2005-04-04

申请人： Ryuichi Kanamura

发明人： Ryuichi Kanamura

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76825 ,  H01L21/76829 ,  Y10S438/942

摘要： Disclosed herein is a production method of a semiconductor device having multilayer interconnections of well-formed dual damascene structure in the low dielectric constant interlayer insulating film. The method includes a step of forming on an underlayer wiring a first insulating film, a second insulating, and first mask forming layer; a step of forming a first resist mask (20) having an inverted pattern of wiring trenches for the upper wiring; a step of etching the first mask forming layer through the first resist mask, thereby forming in the first mask forming layer a concave part conforming to the inverted pattern of wiring trenches for the upper wiring, and then forming on the first mask forming layer a second mask forming layer, thereby filling the concave part with the second mask forming layer; a step of selectively removing the second mask forming layer on the region in which the wiring trench is formed, thereby forming the second mask having the wiring trench pattern; a step of forming on the first mask forming layer a second resist mask (12) having an opening pattern of the via holes; a step of etching the first mask forming layer and the second insulating film through the second resist mask, thereby forming the via holes. This process is followed by the ordinary procedure to form the dual damascene structure.

摘要翻译： 本文公开了一种在低介电常数层间绝缘膜中具有形成良好的双镶嵌结构的多层互连的半导体器件的制造方法。 该方法包括在下层布线上形成第一绝缘膜，第二绝缘和第一掩模形成层的步骤; 形成具有上布线的布线沟槽的倒置图案的第一抗蚀剂掩模（20）的步骤; 通过第一抗蚀剂掩模蚀刻第一掩模形成层的步骤，从而在第一掩模形成层中形成符合上布线的布线沟槽的反转图案的凹部，然后在第一掩模形成层上形成第二掩模形成层 掩模形成层，由此用第二掩模形成层填充凹部; 在形成有布线沟槽的区域上选择性地去除第二掩模形成层的步骤，从而形成具有布线沟槽图案的第二掩模; 在第一掩模形成层上形成具有通孔的开口图案的第二抗蚀剂掩模（12）的步骤; 通过第二抗蚀剂掩模蚀刻第一掩模形成层和第二绝缘膜的步骤，从而形成通孔。 该过程之后是形成双镶嵌结构的普通程序。

公开(公告)号：US06358835B1

公开(公告)日：2002-03-19

申请号：US09501519

申请日：2000-02-09

申请人： Ryuichi Kanamura

发明人： Ryuichi Kanamura

IPC分类号： H01L214763

CPC分类号： H01L21/76838

摘要： During liquid chemical cleaning treatment, leaching of buried plugs occurs from a portion where the buried plugs are exposed locally to result in increase of resistance, lowering of electric conduction yield, lowering of device yield and deterioration of reliability. In a method of manufacturing a semiconductor device by forming upper layer interconnections on buried plugs formed in an interlayer insulating film, the upper layer interconnections are formed by patterning using etching and then plasma processing using an oxygen series gas with addition of a fluorine series gas is applied to the surface of the buried plugs formed being extended out of the upper layer interconnections, before removing the resist film 19 used as an etching mask at least by the organic stripping liquid, thereby forming a protection film on the surface of the buried plugs.

摘要翻译： 在液体化学清洗处理中，埋地塞的浸出发生在埋头塞局部暴露的部分，导致电阻增加，导电率降低，器件产量降低和可靠性恶化。 在通过在层间绝缘膜中形成的掩埋插塞上形成上层布线来制造半导体器件的方法中，通过使用蚀刻进行图案化形成上层布线，然后使用加入氟系气体的氧气气体进行等离子体处理 至少通过有机剥离液除去用作蚀刻掩模的抗蚀剂膜19之前，将所形成的掩埋塞的表面施加到上层互连之外，从而在掩埋塞的表面上形成保护膜。