公开(公告)号：US20050136612A1

公开(公告)日：2005-06-23

申请号：US10780589

申请日：2004-02-19

Applicant: Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen

Inventor： Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen

IPC: H01L21/20 ,  H01L21/268 ,  H01L21/336 ,  H01L29/786 ,  H01L21/76

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L21/268 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78675

Abstract: An amorphous silicon layer is formed on a substrate, and then a protective layer and a reflective layer are formed in turn to form a film stack on portions of the amorphous silicon layer. The reflective layer is a metal material with reflectivity of laser, and the protective layer is able to prevent metal diffusion. When an excimer laser heats the amorphous silicon layer to crystallize the amorphous silicon, nucleation sites are formed in the amorphous silicon layer under the film stack of the protective layer and the reflective layer. Next, laterally expanding crystallization occurs in the amorphous silicon layer to form poly-silicon having crystal grains with size of micrometers and high grain order.

Abstract translation: 在基板上形成非晶硅层，然后依次形成保护层和反射层，以在非晶硅层的部分上形成膜堆叠。 反射层是具有激光反射率的金属材料，保护层能够防止金属扩散。 当准分子激光器加热非晶硅层以使非晶硅结晶时，在保护层和反射层的膜堆叠下面的非晶硅层中形成成核位置。 接下来，在非晶硅层中发生横向膨胀结晶，形成晶粒大小为微米，晶粒度高的多晶硅。

公开(公告)号：US20050073619A1

公开(公告)日：2005-04-07

申请号：US10687759

申请日：2003-10-20

Applicant: Yu-Cheng Chen ,  Chi-Lin Chen

Inventor： Yu-Cheng Chen ,  Chi-Lin Chen

IPC: G09F9/30 ,  G02F1/1362 ,  H01L23/522 ,  H01L27/12 ,  G02F1/136

CPC classification number: H01L27/12 ,  G02F1/136286 ,  H01L23/5221 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-layered complementary wire structure and a manufacturing method thereof are disclosed, comprising a first wire and a second wire. Each of the first and the second wires comprises a main line and a plurality of branch lines located in a different layer from the main line. A plurality contact holes are formed in an insulating layer between the first wire and the second wire to connect the main line of the first wire and the branch lines of the first wire, and connect the main line of the second wire and the branch lines of the second wire. The main line of the first wire is insulated and crossed with the main line of the second wire. The main line of the first wire and the branch lines of the second wire are insulated with each other and located in the same layer. The main line of the second wire and the branch lines of the first wire are insulated with each other and located in the same layer.

Abstract translation: 公开了一种多层互补线结构及其制造方法，包括第一线和第二线。 第一和第二导线中的每一个包括主线和位于与主线不同的层中的多个分支线。 在第一线和第二线之间的绝缘层中形成多个接触孔，以连接第一线的主线和第一线的分支线，并将第二线的主线和 第二根线。 第一根导线的主线绝缘并与第二根导线的主线交叉。 第一线的主线和第二线的分支线彼此绝缘并位于同一层中。 第二线的主线和第一线的分支线彼此绝缘并位于同一层中。

公开(公告)号：US07445972B2

公开(公告)日：2008-11-04

申请号：US11963854

申请日：2007-12-24

Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

IPC: H01L21/00

CPC classification number: H01L29/78696 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/12 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/78675 ,  H01L29/792

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract translation: 提供了适于布置在基板上的存储单元。 存储单元包括多晶硅岛，第一介电层，俘获层，第二介质层和控制栅极。 多硅岛设置在衬底上，并且包括源极区，漏极区和位于源极和漏极区之间的沟道区。 通道区域在其上具有多个规则排列的尖端。 第一介电层设置在多晶硅岛上。 捕获层设置在第一介电层上。 第二介质层设置在捕获层上。 控制栅极设置在第二电介质层上。 上述存储单元可以集成到LTPS-LCD面板或OLED面板中。

公开(公告)号：US20080093604A1

公开(公告)日：2008-04-24

申请号：US11963853

申请日：2007-12-24

Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

IPC: H01L29/786

CPC classification number: H01L29/78696 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/12 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/78675 ,  H01L29/792

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract translation: 提供了适于布置在基板上的存储单元。 存储单元包括多晶硅岛，第一介电层，俘获层，第二介质层和控制栅极。 多硅岛设置在衬底上，并且包括源极区，漏极区和位于源极和漏极区之间的沟道区。 通道区域在其上具有多个规则排列的尖端。 第一介电层设置在多晶硅岛上。 捕获层设置在第一介电层上。 第二介质层设置在捕获层上。 控制栅极设置在第二电介质层上。 上述存储单元可以集成到LTPS-LCD面板或OLED面板中。

公开(公告)号：US07300811B2

公开(公告)日：2007-11-27

申请号：US11164022

申请日：2005-11-08

Applicant: Yu-Cheng Chen ,  Chi-Lin Chen ,  Chi-Ming Chang

Inventor： Yu-Cheng Chen ,  Chi-Lin Chen ,  Chi-Ming Chang

IPC: H01L21/84

CPC classification number: H01L27/1288 ,  G02F1/1368 ,  H01L27/124

Abstract: A multi-layered complementary conductive line structure, a manufacturing method thereof and a manufacturing method of a TFT (thin film transistor) display array are provided. The process of TFT having multi-layered complementary conductive line structures does not need to increase the mask number in comparison with the currently process and is able to solve the resistance problem of the lines inside a display.

Abstract translation: 提供多层互补导电线结构，其制造方法和TFT（薄膜晶体管）显示阵列的制造方法。 具有多层互补导电线结构的TFT的工艺与当前工艺相比不需要增加掩模数，并且能够解决显示器内部的线的电阻问题。

公开(公告)号：US20070099376A1

公开(公告)日：2007-05-03

申请号：US11308710

申请日：2006-04-25

Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

IPC: H01L21/336

CPC classification number: H01L29/78696 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/12 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/78675 ,  H01L29/792

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract translation: 提供了适于布置在基板上的存储单元。 存储单元包括多晶硅岛，第一介电层，俘获层，第二介质层和控制栅极。 多硅岛设置在衬底上，并且包括源极区，漏极区和位于源极和漏极区之间的沟道区。 通道区域在其上具有多个规则排列的尖端。 第一介电层设置在多晶硅岛上。 捕获层设置在第一介电层上。 第二介质层设置在捕获层上。 控制栅极设置在第二电介质层上。 上述存储单元可以集成到LTPS-LCD面板或OLED面板中。

公开(公告)号：US20070020824A1

公开(公告)日：2007-01-25

申请号：US11164022

申请日：2005-11-08

Applicant: Yu-Cheng Chen ,  Chi-Lin Chen ,  Chi-Ming Chang

Inventor： Yu-Cheng Chen ,  Chi-Lin Chen ,  Chi-Ming Chang

IPC: H01L21/84

CPC classification number: H01L27/1288 ,  G02F1/1368 ,  H01L27/124

Abstract: A multi-layered complementary conductive line structure, a manufacturing method thereof and a manufacturing method of a TFT (thin film transistor) display array are provided. The process of TFT having multi-layered complementary conductive line structures does not need to increase the mask number in comparison with the currently process and is able to solve the resistance problem of the lines inside a display.

Abstract translation: 提供多层互补导电线结构，其制造方法和TFT（薄膜晶体管）显示阵列的制造方法。 具有多层互补导电线结构的TFT的工艺与当前工艺相比不需要增加掩模数，并且能够解决显示器内部的线的电阻问题。

公开(公告)号：US08616726B2

公开(公告)日：2013-12-31

申请号：US13306630

申请日：2011-11-29

Applicant: Chi-Lin Chen

Inventor： Chi-Lin Chen

IPC: F21V21/005 ,  F21V21/02

CPC classification number: F21V23/008 ,  F21S4/28 ,  F21V15/013 ,  F21V23/006 ,  F21Y2115/10

Abstract: A LED lamp assembly includes a rectangular electrical box formed of two symmetrical U-shaped frame panels that are detachably fastened together by a tongue-and-groove joint and holding therein a control circuit board that is affixed to two parallel mounting grooves in one U-shaped frame panel by screw nails, a back cover plate and a bracket affixed to the electrical box at two opposite sides for mounting, and an elongated, rectangular light source unit affixed to the bracket and controllable by the control circuit board to emit light.

Abstract translation: LED灯组件包括由两个对称的U形框架板形成的矩形电箱，它们通过榫槽接头可拆卸地紧固在一起，并且在其中保持控制电路板，该控制电路板固定到一个U形框架板中的两个平行的安装槽， 通过螺钉钉形成的框架面板，后盖板和在两个相对侧固定到电箱的支架用于安装，以及细长的矩形光源单元，其固定到支架并由控制电路板控制以发光。

公开(公告)号：US08077139B2

公开(公告)日：2011-12-13

申请号：US12497542

申请日：2009-07-02

Applicant: Shih-Meng Chang ,  Chia-Lin Liu ,  Chi-Neng Mo ,  Ke-Horng Chen ,  Chi-Lin Chen

Inventor： Shih-Meng Chang ,  Chia-Lin Liu ,  Chi-Neng Mo ,  Ke-Horng Chen ,  Chi-Lin Chen

IPC: G09G3/36

CPC classification number: H05B33/0818

Abstract: A driving circuit of a backlight module is provided. The driving circuit has a dimming unit used for transmitting signals, wherein the dimming unit can adjust a current flowing through a light-emitting diode (LED) according a pulse width modulation signal and an enable signal, so as to adjust a light-emitting intensity of the LED. In the present invention, fewer devices are used to implement the dimming unit, and a transmission gate is replaced by a N-type transistor and a P-type transistor, such that a chip area and a circuit cost of the driving circuit are reduced.

Abstract translation: 提供背光模块的驱动电路。 驱动电路具有用于发送信号的调光单元，其中调光单元可以根据脉宽调制信号和使能信号来调节流过发光二极管（LED）的电流，以便调节发光强度 的LED。 在本发明中，使用较少的器件来实现调光单元，并且传输门被N型晶体管和P型晶体管代替，使得驱动电路的芯片面积和电路成本降低。

公开(公告)号：US20110216031A1

公开(公告)日：2011-09-08

申请号：US12814497

申请日：2010-06-14

Applicant: Ke-Horng Chen ,  Shih-Wei Wang ,  Chi-Lin Chen ,  Chih-Chung Chen ,  Chia-Lin Liu ,  Huai-An Li ,  Chi-Neng Mo

Inventor： Ke-Horng Chen ,  Shih-Wei Wang ,  Chi-Lin Chen ,  Chih-Chung Chen ,  Chia-Lin Liu ,  Huai-An Li ,  Chi-Neng Mo

IPC: G06F3/044

CPC classification number: G06F3/044

Abstract: A capacitance sensing circuit for a touch panel includes an analog capacitance-detecting circuit, a PWM-to-digital circuit and a self-calibration circuit. The analog capacitance-detecting circuit detects the capacitance of the touch panel based on a charging current, and converts the detected capacitance into a PWM control signal. The PWM-to-digital circuit converts the PWM control signal into a sensing count value based on a clock signal. The self-calibration circuit adjusts the value of the charging current or the frequency of the clock signal according to the difference between the range of the sensing count value and a predetermined detecting range. The predetermined detecting range can thus be adjusted for matching the range of the sensing count value.

Abstract translation: 用于触摸屏的电容感测电路包括模拟电容检测电路，PWM到数字电路和自校准电路。 模拟电容检测电路基于充电电流检测触摸面板的电容，并将检测到的电容转换为PWM控制信号。 PWM到数字电路基于时钟信号将PWM控制信号转换成感测计数值。 自校准电路根据感测计数值的范围与规定的检测范围的差来调整充电电流的值或时钟信号的频率。 因此可以调整预定的检测范围，以匹配感测计数值的范围。