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    Pixel structure
    1.
    发明授权
    Pixel structure 有权
    像素结构

    公开(公告)号：US07851801B2

    公开(公告)日：2010-12-14

    申请号：US11963853

    申请日：2007-12-24

    Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

    Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

    IPC: H01L29/76

    CPC classification number: H01L29/78696 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/12 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/78675 ,  H01L29/792

    Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

    Abstract translation: 提供了适于布置在基板上的存储单元。 存储单元包括多晶硅岛，第一介电层，俘获层，第二介质层和控制栅极。 多硅岛设置在衬底上，并且包括源极区，漏极区和位于源极和漏极区之间的沟道区。 通道区域在其上具有多个规则排列的尖端。 第一介电层设置在多晶硅岛上。 捕获层设置在第一介电层上。 第二介质层设置在捕获层上。 控制栅极设置在第二电介质层上。 上述存储单元可以集成到LTPS-LCD面板或OLED面板中。

    Thin film transistor structure
    2.
    发明授权
    Thin film transistor structure 有权
    薄膜晶体管结构

    公开(公告)号：US07795683B2

    公开(公告)日：2010-09-14

    申请号：US11561898

    申请日：2006-11-21

    Applicant: Chi-Lin Chen ,  Yu-Cheng Chen ,  Hsing-Hua Wu ,  Po-Tsun Liu

    Inventor： Chi-Lin Chen ,  Yu-Cheng Chen ,  Hsing-Hua Wu ,  Po-Tsun Liu

    IPC: H01L29/04

    CPC classification number: H01L21/268 ,  H01L21/28008 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/66757 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78675 ,  H01L29/78696

    Abstract: A structure of a thin film transistor and a method for making the same are provided. The structure includes a strip-shaped silicon island, a gate, and a first and second ion doping regions. The strip-shaped silicon island is a thin film region with a predetermined long side and short side, and farther has a plurality of lateral grain boundaries substantially parallel to the short side of the silicon island. The gate is located over the silicon island and substantially parallel to the lateral grain boundaries. The first and second ion doping regions, used as source/drain regions of the TFT, are located at two sides along the long side of the island and substantially perpendicular to the gate.

    Abstract translation: 提供薄膜晶体管的结构及其制造方法。 该结构包括条形硅岛，栅极以及第一和第二离子掺杂区域。 带状硅岛是具有预定的长边和短边的薄膜区域，并且还具有基本上平行于硅岛短边的多个横向晶界。 栅极位于硅岛上方并且基本上平行于横向晶界。 用作TFT的源极/漏极区域的第一和第二离子掺杂区域位于岛的长边的两侧并且基本上垂直于栅极。

    Thin Film Transistor (TFT) and Method for Fabricating the Same
    3.
    发明申请
    Thin Film Transistor (TFT) and Method for Fabricating the Same 审中-公开
    薄膜晶体管（TFT）及其制造方法

    公开(公告)号：US20070243670A1

    公开(公告)日：2007-10-18

    申请号：US11279933

    申请日：2006-04-17

    Applicant: Chi-Lin Chen ,  Po-Hao Tsai ,  Hung-Tse Chen ,  Yu-Cheng Chen ,  Jia-Xing Lin

    Inventor： Chi-Lin Chen ,  Po-Hao Tsai ,  Hung-Tse Chen ,  Yu-Cheng Chen ,  Jia-Xing Lin

    IPC: H01L21/84 ,  H01L21/20

    CPC classification number: H01L29/78675 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/2026 ,  H01L27/1281 ,  H01L29/04 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78696

    Abstract: A method for fabricating a thin film transistor (“TFT”) device includes providing a substrate, forming a patterned amorphous silicon layer over the substrate including a pair of first regions, a second region disposed between the pair of first regions, and at least one third region, each of which being disposed between and contiguous with the second region and each of the pair of first regions, the second region including a sub-region contiguous with each of the at least one third region, forming a heat retaining layer over the substrate, irradiating the patterned amorphous silicon layer with a laser through the heat retaining layer to form a patterned crystallized silicon layer corresponding to the patterned amorphous silicon layer including a grain boundary extending substantially across a crystallized sub-region corresponding to the sub-region, and forming a patterned conductive layer over a portion of a crystallized second region of the patterned crystallized silicon layer corresponding to the second region of the patterned amorphous silicon layer.

    Abstract translation: 一种制造薄膜晶体管（“TFT”）器件的方法包括提供衬底，在衬底上形成图案化的非晶硅层，该衬底包括一对第一区域，设置在该对第一区域之间的第二区域和至少一个 第三区域，每个区域设置在第二区域之间并与第二区域和第一区域中的每一个相邻并且与第一区域中的每一个邻接，第二区域包括与至少一个第三区域中的每一个邻接的子区域， 衬底，通过所述保温层用激光照射所述图案化非晶硅层，以形成对应于所述图案化非晶硅层的图案化结晶硅层，所述图案化非晶硅层包括基本上跨越对应于所述子区域的结晶子区域延伸的晶界，以及 在图案化的结晶硅层对角结晶的第二区域的一部分上形成图案化的导电层 结合到图案化非晶硅层的第二区域。

    Method of forming poly-silicon crystallization
    4.
    发明授权
    Method of forming poly-silicon crystallization 有权
    形成多晶硅结晶的方法

    公开(公告)号：US06982195B2

    公开(公告)日：2006-01-03

    申请号：US10780589

    申请日：2004-02-19

    Applicant: Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen

    Inventor： Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen

    IPC: H01L21/84

    CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L21/268 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78675

    Abstract: An amorphous silicon layer is formed on a substrate, and then a protective layer and a reflective layer are formed in turn to form a film stack on portions of the amorphous silicon layer. The reflective layer is a metal material with reflectivity of laser, and the protective layer is able to prevent metal diffusion. When an excimer laser heats the amorphous silicon layer to crystallize the amorphous silicon, nucleation sites are formed in the amorphous silicon layer under the film stack of the protective layer and the reflective layer. Next, laterally expanding crystallization occurs in the amorphous silicon layer to form poly-silicon having crystal grains with size of micrometers and high grain order.

    Abstract translation: 在基板上形成非晶硅层，然后依次形成保护层和反射层，以在非晶硅层的部分上形成膜堆叠。 反射层是具有激光反射率的金属材料，保护层能够防止金属扩散。 当准分子激光器加热非晶硅层以使非晶硅结晶时，在保护层和反射层的膜堆叠下面的非晶硅层中形成成核位置。 接下来，在非晶硅层中发生横向膨胀结晶，形成晶粒大小为微米，晶粒度高的多晶硅。

    Multi-layered complementary wire structure and manufacturing method thereof
    5.
    发明申请
    Multi-layered complementary wire structure and manufacturing method thereof 有权
    多层互补线结构及其制造方法

    公开(公告)号：US20050253249A1

    公开(公告)日：2005-11-17

    申请号：US11131084

    申请日：2005-05-17

    Applicant: Yu-Cheng Chen ,  Chi-Lin Chen

    Inventor： Yu-Cheng Chen ,  Chi-Lin Chen

    IPC: G02F1/1362 ,  H01L21/302 ,  H01L21/31 ,  H01L21/461 ,  H01L21/469 ,  H01L21/8242 ,  H01L23/053 ,  H01L23/12 ,  H01L23/522

    CPC classification number: H01L23/5221 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A multi-layered wire structure includes a substrate, a plurality of first conductive lines formed in a first layer over the substrate extending in parallel to each other in a first direction, a plurality of second conductive lines formed in a second layer over the first layer extending in parallel to each other in a second direction orthogonal to the first direction, a plurality of sets of third conductive lines formed in the second layer extending in the first direction, each set of third conductive lines corresponding to one of the first conductive lines, and a plurality of sets of conductive paths formed between the first layer and the second layer, each set of conductive paths corresponding to one of the first conductive lines and one set of third conductive lines and electrically connecting the corresponding first conductive line to the corresponding set of third conductive lines.

    Abstract translation: 一种多层导线结构，包括：基板，形成在第一层上的多个第一导电线，该第一导电线在基板上沿着第一方向彼此平行地延伸;多个第二导电线，形成在第一层上的第一层 在与第一方向正交的第二方向上彼此平行地延伸的多个第三导线组，所述第二导电线形成在第一方向上延伸，每组第三导线对应于第一导线之一， 以及形成在所述第一层和所述第二层之间的多组导电路径，每组导电路径对应于所述第一导电线中的一条和一组第三导电线，并将相应的第一导电线电连接到相应的集合 的第三导线。

    Fabrication process of memory cell
    6.
    发明授权
    Fabrication process of memory cell 有权
    记忆体的制作过程

    公开(公告)号：US07445972B2

    公开(公告)日：2008-11-04

    申请号：US11963854

    申请日：2007-12-24

    Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

    Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

    IPC: H01L21/00

    CPC classification number: H01L29/78696 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/12 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/78675 ,  H01L29/792

    Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

    Abstract translation: 提供了适于布置在基板上的存储单元。 存储单元包括多晶硅岛，第一介电层，俘获层，第二介质层和控制栅极。 多硅岛设置在衬底上，并且包括源极区，漏极区和位于源极和漏极区之间的沟道区。 通道区域在其上具有多个规则排列的尖端。 第一介电层设置在多晶硅岛上。 捕获层设置在第一介电层上。 第二介质层设置在捕获层上。 控制栅极设置在第二电介质层上。 上述存储单元可以集成到LTPS-LCD面板或OLED面板中。

    PIXEL STRUCTURE
    7.
    发明申请
    PIXEL STRUCTURE 有权
    像素结构

    公开(公告)号：US20080093604A1

    公开(公告)日：2008-04-24

    申请号：US11963853

    申请日：2007-12-24

    Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

    Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

    IPC: H01L29/786

    CPC classification number: H01L29/78696 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/12 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/78675 ,  H01L29/792

    Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

    Abstract translation: 提供了适于布置在基板上的存储单元。 存储单元包括多晶硅岛，第一介电层，俘获层，第二介质层和控制栅极。 多硅岛设置在衬底上，并且包括源极区，漏极区和位于源极和漏极区之间的沟道区。 通道区域在其上具有多个规则排列的尖端。 第一介电层设置在多晶硅岛上。 捕获层设置在第一介电层上。 第二介质层设置在捕获层上。 控制栅极设置在第二电介质层上。 上述存储单元可以集成到LTPS-LCD面板或OLED面板中。

    MEMORY CELL, PIXEL STRUCTURE AND FABRICATION PROCESS OF MEMORY CELL
    9.
    发明申请
    MEMORY CELL, PIXEL STRUCTURE AND FABRICATION PROCESS OF MEMORY CELL 有权
    MEMORY CELL，MEMORY CELL，PIXEL STRUCTURE AND BUABICATION PROCESS OF MEMORY CELL

    公开(公告)号：US20070099376A1

    公开(公告)日：2007-05-03

    申请号：US11308710

    申请日：2006-04-25

    Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

    Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

    IPC: H01L21/336

    CPC classification number: H01L29/78696 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/12 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/78675 ,  H01L29/792

    Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

    Abstract translation: 提供了适于布置在基板上的存储单元。 存储单元包括多晶硅岛，第一介电层，俘获层，第二介质层和控制栅极。 多硅岛设置在衬底上，并且包括源极区，漏极区和位于源极和漏极区之间的沟道区。 通道区域在其上具有多个规则排列的尖端。 第一介电层设置在多晶硅岛上。 捕获层设置在第一介电层上。 第二介质层设置在捕获层上。 控制栅极设置在第二电介质层上。 上述存储单元可以集成到LTPS-LCD面板或OLED面板中。

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