公开(公告)号：US5576644A

公开(公告)日：1996-11-19

申请号：US459874

申请日：1995-06-02

申请人： Antonio R. Pelella

发明人： Antonio R. Pelella

IPC分类号： H03K3/356 ,  H03K5/153

CPC分类号： H03K3/356121 ,  H03K3/356026

摘要： A high speed self-resetting, edge-triggered CMOS (SRCMOS) receiver and parallel L1/L2 latch combination are provided which may be used to receive and latch data from a single-ended input of static random access memory (SRAM) or a dynamic random access memory (DRAM). The invention comprises a true/complement generator circuit (TCG) for generating a data and its complement from a single-ended input, a reset circuit for automatically resetting the TCG independent of the system clock, and a parallel L1/L2 latch for storing the data for further processing. The L1/L2 latch preferably has scan-in and scan-out ports useful for testing and diagnostic purposes.

摘要翻译： 提供高速自复位，边缘触发CMOS（SRCMOS）接收器和并行L1 / L2锁存器组合，可用于从静态随机存取存储器（SRAM）的单端输入或动态 随机存取存储器（DRAM）。 本发明包括用于从单端输入产生数据及其补码的真/补生成电路（TCG），用于独立于系统时钟的TCG自动复位的复位电路和用于存储系统时钟的并行L1 / L2锁存器 数据进一步处理。 L1 / L2锁存器优选地具有用于测试和诊断目的的扫描和扫描输出端口。

公开(公告)号：US5465060A

公开(公告)日：1995-11-07

申请号：US257852

申请日：1994-06-10

申请人： Antonio R. Pelella

发明人： Antonio R. Pelella

IPC分类号： H03K3/356 ,  H03K5/153

CPC分类号： H03K3/356121 ,  H03K3/356026

摘要： A high speed self-resetting, edge-triggered CMOS (SRCMOS) receiver and parallel L1/L2 latch combination are provided which may be used to receive and latch data from a single-ended input of static random access memory (SRAM) or a dynamic random access memory (DRAM). The invention comprises a true/compliment generator circuit (TCG) for generating a data and its compliment from a single-ended input, a reset circuit for automatically resetting the TCG independent of the system clock, and a parallel L1/L2 latch for storing the data for further processing. The L1/L2 latch preferably has scan-in and scan-out ports useful for testing and diagnostic purposes.

摘要翻译： 提供高速自复位，边缘触发CMOS（SRCMOS）接收器和并行L1 / L2锁存器组合，可用于从静态随机存取存储器（SRAM）的单端输入或动态 随机存取存储器（DRAM）。 本发明包括用于从单端输入产生数据及其补码的真实/补码发生器电路（TCG），用于自动重置与系统时钟无关的TCG的复位电路，以及用于存储系统时钟的并行L1 / L2锁存器 数据进一步处理。 L1 / L2锁存器优选地具有用于测试和诊断目的的扫描和扫描输出端口。

公开(公告)号：US5982203A

公开(公告)日：1999-11-09

申请号：US4869

申请日：1998-01-09

申请人： Antonio R. Pelella

发明人： Antonio R. Pelella

IPC分类号： G11C7/06

CPC分类号： G11C7/062

摘要： A high performance "two stage" (or cascading) Self-resetting CMOS (SRCMOS) amplifier where the 2nd stage amplifier is self-timed off of the 1st stage. Also, the SRCMOS nature of this amplifier eliminates the need for additional reset clock signals. The net affect of this invention is that the sensing action of a SRAM cell can start sooner (relative to a single stage sensing scheme) thereby delivering the data to the outputs sooner while providing greater noise immunity when compared to traditional sense amplifiers.

摘要翻译： 高性能“两级”（或级联）自复位CMOS（SRCMOS）放大器，其中第二级放大器自动关闭第一级。 此外，该放大器的SRCMOS特性无需额外的复位时钟信号。 本发明的净影响是SRAM单元的感测动作可以更快（相对于单级感测方案）开始，从而更快地将数据传送到输出端，同时与传统的读出放大器相比，提供更大的抗噪声能力。

公开(公告)号：US5528178A

公开(公告)日：1996-06-18

申请号：US414391

申请日：1995-03-31

申请人： Antonio R. Pelella

发明人： Antonio R. Pelella

IPC分类号： G11C11/419 ,  G11C7/06 ,  H03K19/0948 ,  H03F3/45

CPC分类号： G11C7/065

摘要： A SRCMOS sense amplifier is provided with a latch in the output stage. When a sense amplifier input signal propagates through the circuit and reaches the output stage, a reset signal is generated resetting and charging the input stage and an enable buffer stage of the amplifier to allow the input stage to begin receiving new data while previous data is latched in the output stage. An output stage reset enable is generated when data is at the output terminals of the output stage. The reset enable is combined with a clock signal in a separate output stage reset circuit to reset the circuit on a clocked basis. A further input to the output stage reset circuit is a feedback from a next circuit stage indicating that the data has been properly received in the next stage. The output stage may be reset either in response to the feedback signal from the next stage or in the presence of the reset enable and the clock signal.

摘要翻译： SRCMOS读出放大器在输出级提供锁存器。 当读出放大器输入信号通过电路传播并到达输出级时，复位信号产生复位和充电输入级和放大器的使能缓冲级，以允许输入级开始接收新数据，而先前的数据被锁存 在输出阶段。 当数据位于输出级的输出端时，产生输出级复位使能。 复位使能与单独的输出级复位电路中的时钟信号组合，以便以时钟为基础复位电路。 输出级复位电路的另一输入是来自下一电路级的反馈，指示在下一级中数据已被适当地接收。 可以响应于来自下一级的反馈信号或者存在复位使能和时钟信号来复位输出级。

公开(公告)号：US08638595B2

公开(公告)日：2014-01-28

申请号：US13447600

申请日：2012-04-16

申请人： Antonio R. Pelella

发明人： Antonio R. Pelella

IPC分类号： G11C11/00 ,  G11C5/06 ,  G11C7/10

CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C11/413

摘要： A global to local bit line interface circuit for domino static random access memory (SRAM) devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with write data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and write-around logic configured to directly couple the write data presented on the complementary global write bit lines to read data output circuitry associated with the complementary global read bit lines.

摘要翻译： 用于多米诺骨牌静态随机存取存储器（SRAM）器件的全局到本地位线接口电路包括一对互补的全局写入位线，其通过相应的本地写入位线与SRAM单元的阵列选择性地通信，所述互补的全局写入位线被配置 写入选择的SRAM单元，其中写入数据呈现在一对补充写入数据输入线上; 一对互补的全局读取位线，其通过对应的本地读取位线与SRAM单元的阵列选择性地通信，所述互补的全局读取位线被配置为读取存储在所选择的SRAM单元中的数据，并将读取的数据呈现在一对互补的 读取数据输出行; 以及写入逻辑，被配置为直接将呈现在互补全局写入位线上的写入数据耦合到读取与互补的全局读取位线相关联的数据输出电路。

公开(公告)号：US08184475B2

公开(公告)日：2012-05-22

申请号：US12705780

申请日：2010-02-15

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Antonio R. Pelella ,  Sudesh Saroop

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Antonio R. Pelella ,  Sudesh Saroop

IPC分类号： G11C11/41

CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C11/413 ,  G11C2207/002

摘要： An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which can include first and second pull-down devices for pulling down a respective one of RLBLT and RLBLC at a timing controlled by a write control signal WRT. The circuit can include cross-coupled p-type field effect transistors (“PFETs”) including a first PFET having a gate connected to RLBLT and having a drain connected to RLBLC, and a second PFET of the pair having a gate connected to RLBLC and having a drain connected to RLBLT. A first device can control a strength of the cross-coupled PFETs. A pair of cross-coupled n-type field effect transistors (“NFETs”) can have gates connected to gates of the first and second pull-down devices. A second device can control a strength of the cross-coupled NFETs. The operation of the first and second devices can be controlled by applying first and second signals having programmed levels thereto. The levels of the first and second signals may selectively activate either the first device or the second device, so as to activate either the cross-coupled PFETs or the cross-coupled NFETs at one time.

摘要翻译： 集成电路可以包括具有排列成列的单元的SRAM阵列，每列连接到真实和互补读局部位线RLBLT和RLBLC。 局部位选择电路可以连接到SRAM阵列的列的单元，其可以包括用于在由写控制信号WRT控制的定时下拉RLBLT和RLBLC中的相应一个的第一和第二下拉器件 。 电路可以包括交叉耦合p型场效应晶体管（“PFET”），其包括具有连接到RLBLT并且具有连接到RLBLC的漏极的栅极的第一PFET，并且具有连接到RLBLC的栅极的第二PFET， 漏极连接到RLBLT。 第一器件可以控制交叉耦合PFET的强度。 一对交叉耦合的n型场效应晶体管（“NFET”）可以具有连接到第一和第二下拉器件的栅极的栅极。 第二器件可以控制交叉耦合NFET的强度。 第一和第二装置的操作可以通过向其施加具有编程电平的第一和第二信号来控制。 第一和第二信号的电平可以选择性地激活第一器件或第二器件，以便一次激活交叉耦合的PFET或交叉耦合的NFET。

公开(公告)号：US20110296259A1

公开(公告)日：2011-12-01

申请号：US12787919

申请日：2010-05-26

申请人： Bargav Balakrishnan ,  Pradip Patel ,  Antonio R. Pelella ,  Daniel Rodko

发明人： Bargav Balakrishnan ,  Pradip Patel ,  Antonio R. Pelella ,  Daniel Rodko

IPC分类号： G11C29/12 ,  G06F11/27

CPC分类号： G11C29/08 ,  G06F11/27 ,  G11C11/41 ,  G11C2029/0401

摘要： A method of testing an integrated circuit device, the integrated circuit device having a memory array portion and a logic portion, includes providing test data to the memory array portion of the integrated circuit device using Array Built-In Self Test (ABIST) circuitry; and simultaneously testing the logic portion of the integrated circuit device using the ABIST circuitry, wherein both the memory array portion and the logic portion of the integrated circuit are tested at speed.

摘要翻译： 一种测试集成电路器件的方法，具有存储器阵列部分和逻辑部分的集成电路器件包括使用阵列内置自测（ABIST）电路将测试数据提供给集成电路器件的存储器阵列部分; 并且使用ABIST电路同时测试集成电路器件的逻辑部分，其中存储器阵列部分和集成电路的逻辑部分都以速度进行测试。

公开(公告)号：US20110199817A1

公开(公告)日：2011-08-18

申请号：US12705780

申请日：2010-02-15

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Antonio R. Pelella ,  Sudesh Saroop

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Antonio R. Pelella ,  Sudesh Saroop

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C17/18

CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C11/413 ,  G11C2207/002

摘要： An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which can include first and second pull-down devices for pulling down a respective one of RLBLT and RLBLC at a timing controlled by a write control signal WRT. The circuit can include cross-coupled p-type field effect transistors (“PFETs”) including a first PFET having a gate connected to RLBLT and having a drain connected to RLBLC, and a second PFET of the pair having a gate connected to RLBLC and having a drain connected to RLBLT. A first device can control a strength of the cross-coupled PFETs. A pair of cross-coupled n-type field effect transistors (“NFETs”) can have gates connected to gates of the first and second pull-down devices. A second device can control a strength of the cross-coupled NFETs. The operation of the first and second devices can be controlled by applying first and second signals having programmed levels thereto. The levels of the first and second signals may selectively activate either the first device or the second device, so as to activate either the cross-coupled PFETs or the cross-coupled NFETs at one time.

摘要翻译： 集成电路可以包括具有排列成列的单元的SRAM阵列，每列连接到真实和互补读局部位线RLBLT和RLBLC。 局部位选择电路可以连接到SRAM阵列的列的单元，其可以包括用于在由写控制信号WRT控制的定时下拉RLBLT和RLBLC中的相应一个的第一和第二下拉器件 。 电路可以包括交叉耦合p型场效应晶体管（“PFET”），其包括具有连接到RLBLT并且具有连接到RLBLC的漏极的栅极的第一PFET，并且具有连接到RLBLC的栅极的第二PFET， 漏极连接到RLBLT。 第一器件可以控制交叉耦合PFET的强度。 一对交叉耦合的n型场效应晶体管（“NFET”）可以具有连接到第一和第二下拉器件的栅极的栅极。 第二器件可以控制交叉耦合NFET的强度。 第一和第二装置的操作可以通过向其施加具有编程电平的第一和第二信号来控制。 第一和第二信号的电平可以选择性地激活第一器件或第二器件，以便一次激活交叉耦合的PFET或交叉耦合的NFET。