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公开(公告)号：US08184475B2
公开(公告)日：2012-05-22
申请号：US12705780
申请日：2010-02-15
IPC分类号： G11C11/41
CPC分类号： G11C7/12 , G11C7/18 , G11C11/413 , G11C2207/002
摘要： An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which can include first and second pull-down devices for pulling down a respective one of RLBLT and RLBLC at a timing controlled by a write control signal WRT. The circuit can include cross-coupled p-type field effect transistors (“PFETs”) including a first PFET having a gate connected to RLBLT and having a drain connected to RLBLC, and a second PFET of the pair having a gate connected to RLBLC and having a drain connected to RLBLT. A first device can control a strength of the cross-coupled PFETs. A pair of cross-coupled n-type field effect transistors (“NFETs”) can have gates connected to gates of the first and second pull-down devices. A second device can control a strength of the cross-coupled NFETs. The operation of the first and second devices can be controlled by applying first and second signals having programmed levels thereto. The levels of the first and second signals may selectively activate either the first device or the second device, so as to activate either the cross-coupled PFETs or the cross-coupled NFETs at one time.
摘要翻译： 集成电路可以包括具有排列成列的单元的SRAM阵列，每列连接到真实和互补读局部位线RLBLT和RLBLC。 局部位选择电路可以连接到SRAM阵列的列的单元，其可以包括用于在由写控制信号WRT控制的定时下拉RLBLT和RLBLC中的相应一个的第一和第二下拉器件 。 电路可以包括交叉耦合p型场效应晶体管（“PFET”），其包括具有连接到RLBLT并且具有连接到RLBLC的漏极的栅极的第一PFET，并且具有连接到RLBLC的栅极的第二PFET， 漏极连接到RLBLT。 第一器件可以控制交叉耦合PFET的强度。 一对交叉耦合的n型场效应晶体管（“NFET”）可以具有连接到第一和第二下拉器件的栅极的栅极。 第二器件可以控制交叉耦合NFET的强度。 第一和第二装置的操作可以通过向其施加具有编程电平的第一和第二信号来控制。 第一和第二信号的电平可以选择性地激活第一器件或第二器件，以便一次激活交叉耦合的PFET或交叉耦合的NFET。
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公开(公告)号：US20110199817A1
公开(公告)日：2011-08-18
申请号：US12705780
申请日：2010-02-15
CPC分类号： G11C7/12 , G11C7/18 , G11C11/413 , G11C2207/002
摘要： An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which can include first and second pull-down devices for pulling down a respective one of RLBLT and RLBLC at a timing controlled by a write control signal WRT. The circuit can include cross-coupled p-type field effect transistors (“PFETs”) including a first PFET having a gate connected to RLBLT and having a drain connected to RLBLC, and a second PFET of the pair having a gate connected to RLBLC and having a drain connected to RLBLT. A first device can control a strength of the cross-coupled PFETs. A pair of cross-coupled n-type field effect transistors (“NFETs”) can have gates connected to gates of the first and second pull-down devices. A second device can control a strength of the cross-coupled NFETs. The operation of the first and second devices can be controlled by applying first and second signals having programmed levels thereto. The levels of the first and second signals may selectively activate either the first device or the second device, so as to activate either the cross-coupled PFETs or the cross-coupled NFETs at one time.
摘要翻译： 集成电路可以包括具有排列成列的单元的SRAM阵列，每列连接到真实和互补读局部位线RLBLT和RLBLC。 局部位选择电路可以连接到SRAM阵列的列的单元，其可以包括用于在由写控制信号WRT控制的定时下拉RLBLT和RLBLC中的相应一个的第一和第二下拉器件 。 电路可以包括交叉耦合p型场效应晶体管（“PFET”），其包括具有连接到RLBLT并且具有连接到RLBLC的漏极的栅极的第一PFET，并且具有连接到RLBLC的栅极的第二PFET， 漏极连接到RLBLT。 第一器件可以控制交叉耦合PFET的强度。 一对交叉耦合的n型场效应晶体管（“NFET”）可以具有连接到第一和第二下拉器件的栅极的栅极。 第二器件可以控制交叉耦合NFET的强度。 第一和第二装置的操作可以通过向其施加具有编程电平的第一和第二信号来控制。 第一和第二信号的电平可以选择性地激活第一器件或第二器件，以便一次激活交叉耦合的PFET或交叉耦合的NFET。
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公开(公告)号：US20130289965A1
公开(公告)日：2013-10-31
申请号：US13457722
申请日：2012-04-27
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.
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公开(公告)号：US20130289948A1
公开(公告)日：2013-10-31
申请号：US13611359
申请日：2012-09-12
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.
摘要翻译： 一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。 设备区域提供要分析的感兴趣区域。 生成代表性地包括一个或多个设备区域的部分设备。 通过采用整个装置结构的物理特性来减少部分装置的分析网格。 使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。 还披露了系统。
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公开(公告)号：US08214777B2
公开(公告)日：2012-07-03
申请号：US12419377
申请日：2009-04-07
IPC分类号： G06F17/50
CPC分类号： G01R31/025 , G11C29/006 , G11C29/028 , G11C29/50 , G11C2029/5006 , G11C2029/5602
摘要： A leakage current monitor circuit provides an accurate statistically representative analog of true off-state leakage current in a digital circuit integrated on a die. At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.
摘要翻译： 泄漏电流监测电路在集成在管芯上的数字电路中提供精确的统计代表性的真实截止漏电流的模拟。 与数字电路分离的至少一个N型晶体管和至少一个P型晶体管的尺寸被设计为表示数字电路中相应类型晶体管的总面积。 N型晶体管和P型晶体管的栅极根据数字电路的对应截止状态逻辑电平设置为电压。 N型和P型晶体管形成对应的电流镜电路的一部分，其可以向泄漏电流监视器和/或诸如比较器的控制电路提供输出，所述比较器确定N型或P-型晶体管的漏电流， 类型设备已超过阈值。 测量/控制电路的输出可用于确定集成电路的数字电路或系统环境的温度和/或控制操作。
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6.发明申请Method and System for Determining Element Voltage Selection Control Values for a Storage Device 失效用于确定存储设备的元件电压选择控制值的方法和系统公开(公告)号：US20090132873A1
公开(公告)日：2009-05-21
申请号：US11941161
申请日：2007-11-16
IPC分类号： G11C29/00
CPC分类号： G11C29/006 , G11C11/41 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/72
摘要： A method and system for determining element voltage selection control values for a storage device provides energy conservation in storage arrays while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. At test time, digital control values are determined for selection circuits for each element that set the virtual power supply rail to the minimum power supply voltage, unless a higher power supply voltage is required for the element to meet performance requirements. The set of digital control values can then be programmed into a fuse or used to adjust a mask at manufacture, or supplied on media along with the storage device and loaded into the device at system initialization.
摘要翻译： 用于确定存储设备的元件电压选择控制值的方法和系统在保持特定性能水平的同时在存储阵列中提供节能。 存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。 每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。 在测试时间，除非要求该元件满足性能要求，否则需要为虚拟电源轨设置最小电源电压的每个元件的选择电路确定数字控制值。 然后可以将该组数字控制值编程为保险丝，或者用于在制造时调整掩模，或者随着存储设备一起提供在介质上，并在系统初始化时将其加载到设备中。
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7.发明授权公开(公告)号：US08606557B2
公开(公告)日：2013-12-10
申请号：US12698759
申请日：2010-02-02
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
CPC分类号： G06F17/50
摘要： Techniques for electronic circuit design simulation are provided. In one aspect, a method for electronic circuit design simulation includes the following steps. A model (e.g., a physics-based model) of the circuit design is created. Error tables are created containing data related to one or more regions of the circuit design. The model is modified with data from the error tables. The modified model is used to simulate the circuit design.
摘要翻译： 提供电子电路设计仿真技术。 一方面，电子电路设计仿真的方法包括以下步骤。 创建电路设计的模型（例如，基于物理的模型）。 创建包含与电路设计的一个或多个区域有关的数据的错误表。 该模型使用错误表中的数据进行修改。 修改后的模型用于模拟电路设计。
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公开(公告)号：US08548788B2
公开(公告)日：2013-10-01
申请号：US13609542
申请日：2012-09-11
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F2217/10
摘要： A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design.
摘要翻译： 生成单个有限元网格以预测集成电路设计的性能。 识别多个采样点用于对与集成电路设计相关联的至少一个参数进行变异性研究。 选择采样点以预测由于要用于制造集成电路设计的制造工艺的变化而受到至少一个参数的变化时的集成电路设计的性能。 生成对应于每个采样点的参数化网表。 对每个参数化网表执行技术计算机辅助设计（TCAD）模拟，使用每个参数化网表的单个有限元网格，直到达到收敛，为每个参数化网表获得至少一个度量 指示集成电路设计的性能。 为集成电路设计开发了预测的设计产量。
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公开(公告)号：US20130060551A1
公开(公告)日：2013-03-07
申请号：US13609542
申请日：2012-09-11
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F2217/10
摘要： A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design.
摘要翻译： 生成单个有限元网格以预测集成电路设计的性能。 识别多个采样点用于对与集成电路设计相关联的至少一个参数进行变异性研究。 选择采样点以预测由于要用于制造集成电路设计的制造工艺的变化而受到至少一个参数的变化时的集成电路设计的性能。 生成对应于每个采样点的参数化网表。 对每个参数化网表执行技术计算机辅助设计（TCAD）模拟，使用每个参数化网表的单个有限元网格，直到达到收敛，为每个参数化网表获得至少一个度量 指示集成电路设计的性能。 为集成电路设计开发了预测的设计产量。
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公开(公告)号：US20120293197A1
公开(公告)日：2012-11-22
申请号：US13484868
申请日：2012-05-31
CPC分类号： G01R31/025 , G11C29/006 , G11C29/028 , G11C29/50 , G11C2029/5006 , G11C2029/5602
摘要： At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.
摘要翻译： 与数字电路分离的至少一个N型晶体管和至少一个P型晶体管的尺寸被设计为表示数字电路中相应类型晶体管的总面积。 N型晶体管和P型晶体管的栅极根据数字电路的对应截止状态逻辑电平设置为电压。 N型和P型晶体管形成对应的电流镜电路的一部分，其可以向泄漏电流监视器和/或诸如比较器的控制电路提供输出，所述比较器确定N型或P-型晶体管的漏电流， 类型设备已超过阈值。 测量/控制电路的输出可用于确定集成电路的数字电路或系统环境的温度和/或控制操作。
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