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公开(公告)号：US20130069062A1
公开(公告)日：2013-03-21
申请号：US13233085
申请日：2011-09-15
CPC分类号： H01L22/34 , H01L23/481 , H01L23/58 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits. Also included is a method of testing a semiconductor substrate having a plurality of through substrate vias for current leakage.
摘要翻译： 一种用于通过衬底通孔的泄漏测量结构，其包括半导体衬底; 半导体衬底中的多个穿过衬底通孔，其基本上延伸穿过半导体衬底; 以及位于半导体衬底中的泄漏测量结构。 泄漏测量结构包括延伸到半导体衬底中的多个衬底触点; 多个感测电路，连接到多个通过衬底通孔和多个衬底触点，所述多个感测电路提供指示来自多个通过衬底通孔的电流泄漏的多个输出; 一个内置的自检（BIST）引擎，逐步测试多个通过基板通孔; 以及耦合到BIST引擎以接收来自多个感测电路的输出的存储器。 还包括一种测试半导体衬底的方法，该半导体衬底具有用于电流泄漏的多个通过衬底通孔。
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2.发明授权Method, system and program storage device for simulating electronic device performance as a function of process variations 失效用于模拟电子设备性能的方法，系统和程序存储设备作为过程变化的函数公开(公告)号：US08515715B2
公开(公告)日：2013-08-20
申请号：US13162733
申请日：2011-06-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/10
摘要： Disclosed are embodiments of a method, a system and a program storage device for simulating electronic device performance as a function of process variations. In these embodiments, functions of a primary model parameter for each of multiple secondary model parameters across multiple different process conditions can be determined based on a relatively small number of target sets of device characteristics. These functions can then be used to augment a simulator so that during subsequent simulations of the electronic device over a wide range of varying process conditions, a change in a value for the primary model parameter will automatically result in corresponding changes in values for the secondary model parameters. By augmenting the simulation environment in this manner, the disclosed embodiments efficiently provide more robust simulation results over prior art techniques.
摘要翻译： 公开了用于模拟作为过程变化的函数的电子设备性能的方法，系统和程序存储设备的实施例。 在这些实施例中，可以基于相对较少数量的设备特征的目标集来确定跨越多个不同过程条件的多个辅助模型参数中的每一个的主要模型参数的功能。 这些功能然后可以用于增加模拟器，使得在随后在各种变化的工艺条件下的电子设备的模拟期间，主要模型参数的值的变化将自动导致次级模型的值的相应变化 参数。 通过以这种方式增加仿真环境，所公开的实施例有效地提供了比现有技术更强大的模拟结果。
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公开(公告)号：US08184475B2
公开(公告)日：2012-05-22
申请号：US12705780
申请日：2010-02-15
IPC分类号： G11C11/41
CPC分类号： G11C7/12 , G11C7/18 , G11C11/413 , G11C2207/002
摘要： An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which can include first and second pull-down devices for pulling down a respective one of RLBLT and RLBLC at a timing controlled by a write control signal WRT. The circuit can include cross-coupled p-type field effect transistors (“PFETs”) including a first PFET having a gate connected to RLBLT and having a drain connected to RLBLC, and a second PFET of the pair having a gate connected to RLBLC and having a drain connected to RLBLT. A first device can control a strength of the cross-coupled PFETs. A pair of cross-coupled n-type field effect transistors (“NFETs”) can have gates connected to gates of the first and second pull-down devices. A second device can control a strength of the cross-coupled NFETs. The operation of the first and second devices can be controlled by applying first and second signals having programmed levels thereto. The levels of the first and second signals may selectively activate either the first device or the second device, so as to activate either the cross-coupled PFETs or the cross-coupled NFETs at one time.
摘要翻译： 集成电路可以包括具有排列成列的单元的SRAM阵列，每列连接到真实和互补读局部位线RLBLT和RLBLC。 局部位选择电路可以连接到SRAM阵列的列的单元，其可以包括用于在由写控制信号WRT控制的定时下拉RLBLT和RLBLC中的相应一个的第一和第二下拉器件 。 电路可以包括交叉耦合p型场效应晶体管（“PFET”），其包括具有连接到RLBLT并且具有连接到RLBLC的漏极的栅极的第一PFET，并且具有连接到RLBLC的栅极的第二PFET， 漏极连接到RLBLT。 第一器件可以控制交叉耦合PFET的强度。 一对交叉耦合的n型场效应晶体管（“NFET”）可以具有连接到第一和第二下拉器件的栅极的栅极。 第二器件可以控制交叉耦合NFET的强度。 第一和第二装置的操作可以通过向其施加具有编程电平的第一和第二信号来控制。 第一和第二信号的电平可以选择性地激活第一器件或第二器件，以便一次激活交叉耦合的PFET或交叉耦合的NFET。
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公开(公告)号：US20110199817A1
公开(公告)日：2011-08-18
申请号：US12705780
申请日：2010-02-15
CPC分类号： G11C7/12 , G11C7/18 , G11C11/413 , G11C2207/002
摘要： An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which can include first and second pull-down devices for pulling down a respective one of RLBLT and RLBLC at a timing controlled by a write control signal WRT. The circuit can include cross-coupled p-type field effect transistors (“PFETs”) including a first PFET having a gate connected to RLBLT and having a drain connected to RLBLC, and a second PFET of the pair having a gate connected to RLBLC and having a drain connected to RLBLT. A first device can control a strength of the cross-coupled PFETs. A pair of cross-coupled n-type field effect transistors (“NFETs”) can have gates connected to gates of the first and second pull-down devices. A second device can control a strength of the cross-coupled NFETs. The operation of the first and second devices can be controlled by applying first and second signals having programmed levels thereto. The levels of the first and second signals may selectively activate either the first device or the second device, so as to activate either the cross-coupled PFETs or the cross-coupled NFETs at one time.
摘要翻译： 集成电路可以包括具有排列成列的单元的SRAM阵列，每列连接到真实和互补读局部位线RLBLT和RLBLC。 局部位选择电路可以连接到SRAM阵列的列的单元，其可以包括用于在由写控制信号WRT控制的定时下拉RLBLT和RLBLC中的相应一个的第一和第二下拉器件 。 电路可以包括交叉耦合p型场效应晶体管（“PFET”），其包括具有连接到RLBLT并且具有连接到RLBLC的漏极的栅极的第一PFET，并且具有连接到RLBLC的栅极的第二PFET， 漏极连接到RLBLT。 第一器件可以控制交叉耦合PFET的强度。 一对交叉耦合的n型场效应晶体管（“NFET”）可以具有连接到第一和第二下拉器件的栅极的栅极。 第二器件可以控制交叉耦合NFET的强度。 第一和第二装置的操作可以通过向其施加具有编程电平的第一和第二信号来控制。 第一和第二信号的电平可以选择性地激活第一器件或第二器件，以便一次激活交叉耦合的PFET或交叉耦合的NFET。
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公开(公告)号：US08692246B2
公开(公告)日：2014-04-08
申请号：US13233085
申请日：2011-09-15
CPC分类号： H01L22/34 , H01L23/481 , H01L23/58 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits. Also included is a method of testing a semiconductor substrate.
摘要翻译： 一种用于通过衬底通孔的泄漏测量结构，其包括半导体衬底; 半导体衬底中的多个穿过衬底通孔，其基本上延伸穿过半导体衬底; 以及位于半导体衬底中的泄漏测量结构。 泄漏测量结构包括延伸到半导体衬底中的多个衬底触点; 多个感测电路，连接到多个通过衬底通孔和多个衬底触点，所述多个感测电路提供指示来自多个通过衬底通孔的电流泄漏的多个输出; 一个内置的自检（BIST）引擎，逐步测试多个通过基板通孔; 以及耦合到BIST引擎以接收来自多个感测电路的输出的存储器。 还包括测试半导体衬底的方法。
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6.发明申请METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR SIMULATING ELECTRONIC DEVICE PERFORMANCE AS A FUNCTION OF PROCESS VARIATIONS 失效用于模拟电子设备性能的方法，系统和程序存储设备作为过程变化的功能公开(公告)号：US20120323548A1
公开(公告)日：2012-12-20
申请号：US13162733
申请日：2011-06-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/10
摘要： Disclosed are embodiments of a method, a system and a program storage device for simulating electronic device performance as a function of process variations. In these embodiments, functions of a primary model parameter for each of multiple secondary model parameters across multiple different process conditions can be determined based on a relatively small number of target sets of device characteristics. These functions can then be used to augment a simulator so that during subsequent simulations of the electronic device over a wide range of varying process conditions, a change in a value for the primary model parameter will automatically result in corresponding changes in values for the secondary model parameters. By augmenting the simulation environment in this manner, the disclosed embodiments efficiently provide more robust simulation results over prior art techniques.
摘要翻译： 公开了用于模拟作为过程变化的函数的电子设备性能的方法，系统和程序存储设备的实施例。 在这些实施例中，可以基于相对较少数量的设备特征的目标集来确定跨越多个不同过程条件的多个辅助模型参数中的每一个的主要模型参数的功能。 这些功能然后可以用于增加模拟器，使得在随后在各种变化的工艺条件下的电子设备的模拟期间，主要模型参数的值的变化将自动导致次级模型的值的相应变化 参数。 通过以这种方式增加仿真环境，所公开的实施例有效地提供了比现有技术更强大的模拟结果。
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