公开(公告)号：US07939413B2

公开(公告)日：2011-05-10

申请号：US11297522

申请日：2005-12-08

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Brian Joseph Greene ,  Kern Rim

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Brian Joseph Greene ,  Kern Rim

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses. The S/D stressor regions can be thicker adjacent to the gate structure than adjacent to the isolation regions; We implant dopant ions into the S/D stressor regions and into the substrate below the S/D stressor regions adjacent to the isolation regions to form upper stressor doped regions.

摘要翻译： 示例性实施例是用于形成具有嵌入的应力源S / D区域（例如，SiGe）的FET的结构和方法，位于与隔离区域相邻的嵌入式S / D区域下方的掺杂层，以及FET上减少的间隔物上的应力衬垫 门。 包括以下的示例性方法。 我们在衬底的第一区域上提供栅极结构。 栅极结构由栅极电介质，栅极和侧壁间隔物组成。 我们提供与栅极结构间隔开的第一区域中的隔离区域; 以及栅极结构下的衬底中的沟道区。 我们在邻近侧壁间隔物的衬底的第一区域中形成S / D凹槽。 形成填充S / D凹槽的S / D应力区域。 与隔离区相邻的S / D应力区可以比栅极结构更厚; 我们将掺杂剂离子注入到S / D应力区域中并进入与隔离区域相邻的S / D应力区域下方的衬底中以形成上部应力源掺杂区域。

公开(公告)号：US07772071B2

公开(公告)日：2010-08-10

申请号：US11383951

申请日：2006-05-17

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.

摘要翻译： 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

公开(公告)号：US07572712B2

公开(公告)日：2009-08-11

申请号：US11561982

申请日：2006-11-21

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson R. Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson R. Holt

IPC分类号： H01L21/76

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/78639

摘要： Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region under a channel region of an FET. In a second example embodiment, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions of an FET. In a third example embodiment, both PFET and NFET devices are formed. In the PFET device, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions. In the NFET device, the lateral epitaxial layer is formed over a stressor region under a channel region of the NFET.

摘要翻译： 通过在源极/漏极区域或沟道区域之下形成应力区域并且在应力区域上使用横向外延形成选择性应变Si，从而在通道区域上具有应力的FET器件的实施例。 在第一示例性实施例中，在FET的沟道区之下的应力区域上形成横向外延层。 在第二示例性实施例中，在FET的源极/漏极区域之下的S / D应力区域上形成横向S / D外延层。 在第三示例性实施例中，形成PFET和NFET器件。 在PFET器件中，在源极/漏极区域之下的S / D应力区域上形成横向S / D外延层。 在NFET器件中，横向外延层形成在NFET的沟道区下方的应力区域上。

公开(公告)号：US08912567B2

公开(公告)日：2014-12-16

申请号：US12852995

申请日：2010-08-09

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66628 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.

摘要翻译： 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

公开(公告)号：US20080116482A1

公开(公告)日：2008-05-22

申请号：US11561982

申请日：2006-11-21

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson R. Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson R. Holt

IPC分类号： H01L27/092 ,  H01L29/778 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/78639

摘要： Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region under a channel region of an FET. In a second example embodiment, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions of an FET. In a third example embodiment, both PFET and NFET devices are formed. In the PFET device, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions. In the NFET device, the lateral epitaxial layer is formed over a stressor region under a channel region of the NFET.

摘要翻译： 通过在源极/漏极区域或沟道区域之下形成应力区域并且在应力区域上使用横向外延形成选择性应变Si，从而在通道区域上具有应力的FET器件的实施例。 在第一示例性实施例中，在FET的沟道区之下的应力区域上形成横向外延层。 在第二示例性实施例中，在FET的源极/漏极区域之下的S / D应力区域上形成横向S / D外延层。 在第三示例性实施例中，形成PFET和NFET器件。 在PFET器件中，在源极/漏极区域之下的S / D应力区域上形成横向S / D外延层。 在NFET器件中，横向外延层形成在NFET的沟道区下方的应力区域上。

公开(公告)号：US20070267703A1

公开(公告)日：2007-11-22

申请号：US11383951

申请日：2006-05-17

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

IPC分类号： H01L29/94

CPC分类号： H01L29/66628 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.

摘要翻译： 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

公开(公告)号：US09356025B2

公开(公告)日：2016-05-31

申请号：US14348579

申请日：2012-03-29

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66

CPC分类号： H01L27/092 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66575 ,  H01L29/7846

摘要： The present invention relates to enhancing MOSFET performance with the corner stresses of STI. A method of manufacturing a MOS device comprises the steps of: providing a semiconductor substrate; forming trenches on the semiconductor substrate and at least a pMOS region and at least an nMOS region surrounded by the trenches; filling the trenches with a dielectric material having a stress; removing at least the dielectric material having a stress in the trenches which is adjacent to a position where a channel is to be formed on each of the pMOS and nMOS regions so as to form exposed regions; filling the exposed regions with a insulating material; and forming pMOS and nMOS devices on the pMOS region and the nMOS region, respectively, wherein each of the pMOS and nMOS devices comprises a channel, a gate formed above the channel, and a source and a drain formed at both sides of the channel; wherein in a channel length direction, the boundary of each exposed region is substantially aligned with the boundary of the position of the channel, or the boundary of each exposed region extends along the channel length direction to be aligned with the boundary of corresponding pMOS or nMOS region.

摘要翻译： 本发明涉及利用STI的拐角应力来增强MOSFET的性能。 一种制造MOS器件的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底和至少一个pMOS区域和由所述沟槽包围的至少nMOS区域中形成沟槽; 用具有应力的介电材料填充沟槽; 至少去除在沟道中具有应力的介电材料，所述沟槽邻近要在pMOS和nMOS区域中的每一个上形成沟道的位置，以形成暴露区域; 用绝缘材料填充暴露的区域; 以及分别在pMOS区域和nMOS区域上形成pMOS和nMOS器件，其中pMOS和nMOS器件中的每一个包括沟道，形成在沟道上方的栅极以及形成在沟道两侧的源极和漏极; 其中在通道长度方向上，每个曝光区域的边界基本上与通道位置的边界对齐，或者每个曝光​​区域的边界沿着沟道长度方向延伸以与对应的pMOS或nMOS的边界对准 地区。

公开(公告)号：US09054221B2

公开(公告)日：2015-06-09

申请号：US13510807

申请日：2011-11-18

申请人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer; a plurality of MOSFETs being formed adjacently to each other in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate; and a plurality of shallow trench isolations, each of which being formed between respective adjacent MOSFETs to isolate the respective adjacent MOSFETs from each other, wherein the respective adjacent MOSFETs share a common backgate isolation region under and in direct contact with the respective backgate in the semiconductor substrate, and a PNP junction or an NPN junction is formed by the common backgate isolation region and the respective backgate of the respective adjacent MOSFETs. According to the present disclosure, respective backgates of two adjacent MOSFETs are isolated from each other by the shallow trench isolation. Furthermore, the two adjacent MOSFETs are also isolated from each other by the PNP or NPN junction formed by the respective backgates of the two adjacent MOSFETs and the common backgate isolation. As a result, this device structure has a better insulation effect over the prior art MOSFET and it greatly reduces the possibility of breakthrough.

摘要翻译： 本发明提供一种半导体器件及其制造方法。 半导体器件包括：SOI晶片，其包括半导体衬底，掩埋绝缘层和半导体层，其中所述掩埋绝缘层设置在所述半导体衬底上，并且所述半导体层设置在所述掩埋绝缘层上; 在SOI晶片中彼此相邻形成的多个MOSFET，其中每个MOSFET包括形成在半导体衬底中的相应后栅; 以及多个浅沟槽隔离，其中每一个均形成在各个相邻的MOSFET之间，以将各个相邻的MOSFET彼此隔离，其中相应的相邻MOSFET在半导体内部和相应的后栅极直接接触并与之直接接触。 衬底，并且PNP结或NPN结由公共背栅隔离区和相应的相邻MOSFET的相应背栅形成。 根据本公开，两个相邻MOSFET的相应背板通过浅沟槽隔离彼此隔离。 此外，两个相邻的MOSFET也通过由两个相邻MOSFET的相应后沿和公共背栅隔离形成的PNP或NPN结彼此隔离。 结果，该器件结构具有比现有技术的MOSFET更好的绝缘效果，并且大大降低了突破的可能性。

公开(公告)号：US08981454B2

公开(公告)日：2015-03-17

申请号：US13061461

申请日：2010-09-25

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L29/788 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/845 ,  H01L29/42324 ,  H01L29/785 ,  H01L29/7881

摘要： The present application discloses a non-volatile memory device, comprising a semiconductor fin on an insulating layer; a channel region at a central portion of the semiconductor fin; source/drain regions on both sides of the semiconductor fin; a floating gate arranged at a first side of the semiconductor fin and extending in a direction further away from the semiconductor fin; and a first control gate arranged on top of the floating gate or covering top and sidewall portions of the floating gate. The non-volatile memory device reduces a short channel effect, has an increased memory density, and is cost effective.

摘要翻译： 本申请公开了一种非易失性存储器件，其包括绝缘层上的半导体鳍片; 在半导体鳍片的中心部分处的沟道区域; 半导体鳍片两侧的源极/漏极区域; 布置在半导体鳍片的第一侧并沿远离半导体鳍片的方向延伸的浮动栅极; 以及布置在所述浮动栅极的顶部上或覆盖所述浮动栅极的顶部和侧壁部分的第一控制栅极。 非易失性存储器件减少短通道效应，具有增加的存储器密度，并且是成本有效的。

公开(公告)号：US08952453B2

公开(公告)日：2015-02-10

申请号：US13580053

申请日：2011-11-18

申请人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Qingqing Liang ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/78648

摘要： The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks.

摘要翻译： 本申请公开了一种MOSFET及其制造方法。 MOSFET形成在SOI晶片上，包括：用于限定半导体层中的有源区的浅沟槽隔离; 半导体层上的栅极堆叠; 栅极堆叠的两侧的半导体层中的源极区域和漏极区域; 半导体层中的沟道区，被源极区和漏极区夹持; 半导体衬底中的背栅; 与半导体层和浅沟槽隔离之间的边界重叠的第一虚拟栅极堆叠; 以及在浅沟槽隔离上的第二虚拟栅极堆叠，其中所述MOSFET还包括多个导电通孔，所述多个导电通孔设置在所述栅极堆叠和所述第一伪栅极堆叠之间，并分别电连接到所述源极区域和所述漏极区域之间，以及 第一虚拟栅极堆叠和第二虚拟栅极堆叠并且电连接到背栅极。 MOSFET通过虚拟栅极堆叠避免了背栅极和源极/漏极区域之间的短路。