公开(公告)号：US07939413B2

公开(公告)日：2011-05-10

申请号：US11297522

申请日：2005-12-08

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Brian Joseph Greene ,  Kern Rim

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Brian Joseph Greene ,  Kern Rim

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses. The S/D stressor regions can be thicker adjacent to the gate structure than adjacent to the isolation regions; We implant dopant ions into the S/D stressor regions and into the substrate below the S/D stressor regions adjacent to the isolation regions to form upper stressor doped regions.

摘要翻译： 示例性实施例是用于形成具有嵌入的应力源S / D区域（例如，SiGe）的FET的结构和方法，位于与隔离区域相邻的嵌入式S / D区域下方的掺杂层，以及FET上减少的间隔物上的应力衬垫 门。 包括以下的示例性方法。 我们在衬底的第一区域上提供栅极结构。 栅极结构由栅极电介质，栅极和侧壁间隔物组成。 我们提供与栅极结构间隔开的第一区域中的隔离区域; 以及栅极结构下的衬底中的沟道区。 我们在邻近侧壁间隔物的衬底的第一区域中形成S / D凹槽。 形成填充S / D凹槽的S / D应力区域。 与隔离区相邻的S / D应力区可以比栅极结构更厚; 我们将掺杂剂离子注入到S / D应力区域中并进入与隔离区域相邻的S / D应力区域下方的衬底中以形成上部应力源掺杂区域。

公开(公告)号：US20080283934A1

公开(公告)日：2008-11-20

申请号：US12182212

申请日：2008-07-30

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC分类号： H01L29/78 ,  H01L21/44

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.

摘要翻译： 公开了具有用于接触的大致L形硅化物元件的结构，半导体器件和方法。 基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。 在一个实施例中，该结构包括基本上为L形的硅化物元件，其包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面 直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。 触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。 可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

公开(公告)号：US08643119B2

公开(公告)日：2014-02-04

申请号：US12182212

申请日：2008-07-30

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC分类号： H01L29/76

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for a semiconductor device, according to an embodiment, includes: a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element.

摘要翻译： 根据实施例的用于半导体器件的结构包括：基本上L形的硅化物元件，其包括基底构件和延伸构件，其中所述基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得 基部构件的基本水平的表面直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。

公开(公告)号：US07718500B2

公开(公告)日：2010-05-18

申请号：US11305584

申请日：2005-12-16

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Judson Robert Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Judson Robert Holt

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.

摘要翻译： 用于在NFET器件中形成凸起的源极/漏极结构并在PFET器件中形成嵌入的SiGe源极/漏极的结构和方法。 我们在衬底上的NFET区域和PFET区域上的PFET栅极结构提供NFET栅极结构。 我们提供与NFET栅极相邻的NFET SDE区域，并提供与PFET栅极相邻的PFET SDE区域。 我们在邻近PFET第二间隔物的衬底中的PFET区域中形成凹陷。 我们在凹槽中形成PFET嵌入式源极/漏极应力器。 我们在NFET SDE区域上形成NFET S / D外延Si层，并在PFET嵌入式源极/漏极应力器上形成PFET S / D外延Si层。 在随后的自对准硅化物步骤中，在PFET嵌入式源极/漏极应力源上的外延Si层被消耗，以在PFET嵌入式源极/漏极应力器上形成稳定和低电阻率的硅化物。 我们通过将N型离子注入到与NFET栅极结构相邻的NFET区域中并进入NFET S / D应力Si层来形成NFET S / D注入，以形成升高的NFET源极/漏极。

公开(公告)号：US20070267753A1

公开(公告)日：2007-11-22

申请号：US11383965

申请日：2006-05-18

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.

摘要翻译： 公开了具有用于接触的大致L形硅化物元件的结构，半导体器件和方法。 基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。 在一个实施例中，该结构包括基本上为L形的硅化物元件，其包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面 直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。 触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。 可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

公开(公告)号：US08288825B2

公开(公告)日：2012-10-16

申请号：US12780962

申请日：2010-05-17

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Judson Robert Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Judson Robert Holt

IPC分类号： H01L21/70

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.

摘要翻译： 用于在NFET器件中形成凸起的源极/漏极结构并在PFET器件中形成嵌入的SiGe源极/漏极的结构和方法。 我们在衬底上的NFET区域和PFET区域上的PFET栅极结构提供NFET栅极结构。 我们提供与NFET栅极相邻的NFET SDE区域，并提供与PFET栅极相邻的PFET SDE区域。 我们在邻近PFET第二间隔物的衬底中的PFET区域中形成凹陷。 我们在凹槽中形成PFET嵌入式源极/漏极应力器。 我们在NFET SDE区域上形成NFET S / D外延Si层，并在PFET嵌入式源极/漏极应力器上形成PFET S / D外延Si层。 在随后的自对准硅化物步骤中，在PFET嵌入式源极/漏极应力源上的外延Si层被消耗，以在PFET嵌入式源极/漏极应力器上形成稳定和低电阻率的硅化物。 我们通过将N型离子注入到与NFET栅极结构相邻的NFET区域中并进入NFET S / D应力Si层来形成NFET S / D注入，以形成升高的NFET源极/漏极。

公开(公告)号：US07442619B2

公开(公告)日：2008-10-28

申请号：US11383965

申请日：2006-05-18

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC分类号： H01L21/283 ,  H01L23/482

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the substantially L-shaped silicide element includes a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.

摘要翻译： 公开了一种制造具有形成接触的大致L形硅化物元件的半导体器件的方法。 基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。 在一个实施例中，基本上L形的硅化物元件包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面直接接触 STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。 触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。 可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

公开(公告)号：US07566609B2

公开(公告)日：2009-07-28

申请号：US11164568

申请日：2005-11-29

申请人： Zhijiong Luo ,  Yung Fu Chong ,  Huilong Zhu

发明人： Zhijiong Luo ,  Yung Fu Chong ,  Huilong Zhu

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

摘要： There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, conductive layers and an insulating layer. Forming said gate structure includes a step of recessing the conductive layer in the gate structure, and the steps of recessing the conductive layer and forming the recess in the substrate are performed in a single step. There is also provided a FET device.

摘要翻译： 提供了一种制造场效应晶体管（FET）的方法，该方法包括以下步骤：在半导体衬底上形成栅极结构，并在衬底中形成凹陷并将第二半导体材料嵌入凹槽中。 栅极结构包括栅极电介质层，导电层和绝缘层。 形成所述栅极结构包括使栅极结构中的导电层凹陷的步骤，并且在单个步骤中执行使导电层凹陷并且在衬底中形成凹部的步骤。 还提供了一种FET器件。

公开(公告)号：US20070293016A1

公开(公告)日：2007-12-20

申请号：US11424076

申请日：2006-06-14

申请人： Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Phung T. Nguyen ,  William C. Wille ,  Richard Lindsay ,  Zhao Lun ,  Yung Fu Chong ,  Siddhartha Panda

发明人： Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Phung T. Nguyen ,  William C. Wille ,  Richard Lindsay ,  Zhao Lun ,  Yung Fu Chong ,  Siddhartha Panda

IPC分类号： H01L21/76

CPC分类号： H01L21/823892 ,  H01L21/76218 ,  H01L21/76232 ,  H01L21/823878

摘要： A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.

摘要翻译： 半导体结构包括具有位于其中的掺杂区的基极半导体衬底和位于掺杂区上方的外延区。 半导体结构还包括位于掺杂区和外延区的最后隔离区。 最后的隔离区域在掺杂区域内具有比外延区域内更大的线宽。 制造半导体结构的方法提供了在外延区之前形成掺杂区。 掺杂区域可以形成为具有减少的良好注入能量和减小的横向分层。 具有可变线宽的最终隔离区域提供比实际沟槽隔离深度更大的有效隔离深度。

公开(公告)号：US08912567B2

公开(公告)日：2014-12-16

申请号：US12852995

申请日：2010-08-09

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66628 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.

摘要翻译： 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。