公开(公告)号：US5497497A

公开(公告)日：1996-03-05

申请号：US51601

申请日：1993-04-22

Applicant: David A. Miller ,  Kenneth A. Jansen ,  Montgomery C. McGraw ,  Darren J. Cepulis

Inventor： David A. Miller ,  Kenneth A. Jansen ,  Montgomery C. McGraw ,  Darren J. Cepulis

IPC: G06F9/445 ,  G06F11/14 ,  G06F11/20 ,  G06F11/22 ,  G06F9/40 ,  G06F9/42 ,  G06F11/34

CPC classification number: G06F11/1417 ,  G06F11/22 ,  G06F11/2284 ,  G06F15/177 ,  G06F9/4403 ,  G06F9/4405 ,  G06F11/2038 ,  G06F11/2043 ,  G06F9/4416

Abstract: Two design variations which allow multiple processors to start up using a single ROM. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.

Abstract translation: 两种设计变化，允许多个处理器使用单个ROM启动。 在每个设计中，允许单个主处理器执行完整的POST，而剩余的辅助处理器在其POST过程中被引导以执行更有限的初始化序列。 上电时，主处理器开始正常POST，而辅助处理器保持，直到向量放置到重定向向量位置。 然后，使用其位于由重定向向量指示的地址处的自己的初始化代码随后启动每个二级处理器。 第一种技术适用于一般的多处理器系统，因为这种设计的实现可以从外部软件运行，也可以从添加到正在使用它的特定机器的操作系统运行。 第二种技术更具体地针对特定系统，并且包括使用身份寄存器来区分主处理器和辅助处理器。

公开(公告)号：US5493203A

公开(公告)日：1996-02-20

申请号：US376129

申请日：1995-01-19

Applicant: Scott W. Dalton

Inventor： Scott W. Dalton

IPC: G05F1/445 ,  G05F1/44

CPC classification number: G05F1/445

Abstract: A low quiescent current voltage regulator particularly suited for providing current to the RTC/CMOS memory section of a notebook computer. The gate of the JFET is grounded, the drain connected to the main battery and the source connected to the RTC voltage input of the RTC/CMOS memory section. The JFET source voltage approaches the gate-source cutoff voltage of the JFET. This cutoff voltage is selected to be in the proper range for the RTC/CMOS memory section. A complete RTC voltage control circuit is configured to provide 5 volts from the system voltage when the computer is turned on, 3 to 5 volts from the JFET when the computer is turned off and the main battery is present and 3 volts from the RTC battery when the computer is turned off and the main battery is removed.

Abstract translation: 一种低静态电流稳压器，特别适用于向笔记本电脑的RTC / CMOS存储器部分提供电流。 JFET的栅极接地，漏极连接到主电池，源极连接到RTC / CMOS存储器部分的RTC电压输入。 JFET源极电压接近JFET的栅极 - 源极截止电压。 该截止电压被选择在RTC / CMOS存储器部分的适当范围内。 完整的RTC电压控制电路被配置为当计算机打开时从系统电压提供5伏特，当计算机关闭并且存在主电池并且来自RTC电池的电压为3伏时，从JFET 3至5伏特 计算机已关闭，主电池已取出。

公开(公告)号：US5471590A

公开(公告)日：1995-11-28

申请号：US188456

申请日：1994-01-28

Applicant: Maria L. Melo ,  Randy M. Bonella

Inventor： Maria L. Melo ,  Randy M. Bonella

IPC: G06F13/362 ,  G06F13/364 ,  G06F13/36

CPC classification number: G06F13/364

Abstract: An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.

Abstract translation: 仲裁器允许重试请求在随后的仲裁中具有高优先级，不通过对总线的授权但中止的访问改变优先级，而且防止被中止的请求者通过屏蔽其总线请求信号来捶打总线，直到数据可用。 此外，如果重试对主存储器的访问，则除了来自存储器系统的总线请求之外的所有总线请求都被屏蔽，以便为存储器系统提供最高的有效优先级，以允许发生任何冲洗操作。 各种总线请求的掩蔽允许仲裁器控制对PCI标准总线的访问，而不需要添加特定的信号。 仲裁者还包括修改的优先级LRU技术，并且如果重试则提供具有附加最高优先级位置的锁定请求者。

公开(公告)号：US5463743A

公开(公告)日：1995-10-31

申请号：US160585

申请日：1993-12-01

Applicant: William C. Galloway

Inventor： William C. Galloway

IPC: G06F13/12 ,  G06F13/10

CPC classification number: G06F13/126

Abstract: A method for improving SCSI controller operations by actively patching SCSI processor instructions. In a first case, tag values assigned to queues for tagged queue operation are a multiple of the SCSI processor jump instruction length. When reselected, the tag value is patched or overwritten as the least significant byte of the address of a jump instruction. The upper bytes point to the beginning of a jump table. Each entry in the jump table is a jump instruction to the sequence for a particular queue or thread. Thus simple entry is made to the desired thread without a conditional branch tree. In a second case, special SCSI operations are directly handled by the host device driver and the SCSI processor only performs conventional data transfers and similar operations. The device driver patches the message length of the SCSI processor code to an illegal value, so that an illegal instruction develops, prompting the host device driver to perform the operation at a register level. This approach allows removal of all special operation conditional branching from the SCSI processor, greatly speeding up operations.

Abstract translation: 通过主动修补SCSI处理器指令来改进SCSI控制器操作的方法。 在第一种情况下，分配给用于标记队列操作的队列的标签值是SCSI处理器跳转指令长度的倍数。 当重新选择时，标签值被修补或重写为跳转指令的地址的最低有效字节。 高字节指向跳转表的开头。 跳转表中的每个条目是针对特定队列或线程的序列的跳转指令。 因此，在没有条件分支树的情况下，对所需的线程进行简单的输入。 在第二种情况下，专用SCSI操作由主机设备驱动程序直接处理，SCSI处理器仅执行常规数据传输和类似操作。 设备驱动程序将SCSI处理器代码的消息长度修补为非法值，从而开发非法指令，提示主机设备驱动程序在注册级执行操作。 这种方法允许从SCSI处理器中移除所有特殊操作条件分支，大大加快了操作。

公开(公告)号：US5442753A

公开(公告)日：1995-08-15

申请号：US163165

申请日：1993-12-07

Applicant: Timothy K. Waldrop ,  Paul R. Culley

Inventor： Timothy K. Waldrop ,  Paul R. Culley

IPC: G06F3/06 ,  G06F5/06 ,  G06F13/28 ,  G06F9/455

CPC classification number: G06F3/0601 ,  G06F13/28 ,  G06F5/06 ,  G06F2003/0692

Abstract: The present invention includes two variations of an apparatus which generate a version of the IORC* bus signal that is supplied to the read strobe input of a floppy disk controller that is asserted at the appropriate time during verify cycles between the floppy disk controller and a DMA controller. These designs allow an 82077 floppy disk controller to operate properly in FIFO mode when it is being used with software that does not require generation of this signal. The designs include use of a PAL and certain bus signal inputs to generate a signal which is asserted at the appropriate times during verify transfers. This signal is combined with the regular IORC* bus signal to produce the signal that is provided to the read strobe input of the floppy disk controller.

Abstract translation: 本发明包括一种装置的两个变体，该装置产生提供给软盘控制器的读选通输入的IORC *总线信号的版本，该软盘控制器在软盘控制器和DMA之间的验证周期期间在适当的时间被断言 控制器。 这些设计允许82077软盘控制器在与不需要生成此信号的软件一起使用时，以FIFO模式正常运行。 这些设计包括使用PAL和某些总线信号输入来产生在验证传输期间在适当时间被断言的信号。 该信号与常规IORC *总线信号组合，以产生提供给软盘控制器的读选通输入的信号。

公开(公告)号：US5325511A

公开(公告)日：1994-06-28

申请号：US121978

申请日：1993-09-14

Applicant: Michael J. Collins ,  Roger E. Tipley

Inventor： Michael J. Collins ,  Roger E. Tipley

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/00 ,  G06F12/02

CPC classification number: G06F12/123 ,  G06F12/0831

Abstract: An apparatus for performing Least Recently Used techniques for a four way set associative cache system which includes a random access memory (RAM) which stores the ways representing the least recently used (LRU), most recently used (MRU) and LRU+1. The MRU-1 is developed by XORing the other three LRU way information values. Processor or snoop operation is determined and the way use aging information valued is based on snooping or processor operations. For processor operations the accessed or to be accessed way is set as the MRU, while in snoop operations, the way being accessed is set as the LRU. The aging of the remaining ways is shuffled accordingly. This shuffling occurs each cycle but is only stored on processor cache hit, processor read cache miss and snoop hit operations.

Abstract translation: 一种用于对四路组相关高速缓存系统执行最近最近使用的技术的装置，其包括存储表示最近使用的最近使用（LRU）的方式的随机存取存储器（RAM），最近使用的（MRU）和LRU + 1。 MRU-1是通过异或其他三个LRU方式信息值来开发的。 处理器或窥探操作被确定，使用老化信息的方法是基于窥探或处理器操作。 对于处理器操作，访问或被访问的方式被设置为MRU，而在窥探操作中，被访问的方式设置为LRU。 其余方式的衰老相应地洗牌。 这种混洗发生在每个周期，但只存储在处理器缓存命中，处理器读取高速缓存未命中和窥探命中操作。

公开(公告)号：US5226122A

公开(公告)日：1993-07-06

申请号：US88093

申请日：1987-08-21

Applicant: John S. Thayer ,  Montgomery C. McGraw

Inventor： John S. Thayer ,  Montgomery C. McGraw

IPC: G06F3/023 ,  G06F9/30 ,  G06F9/318 ,  G06F9/355

CPC classification number: G06F9/30189 ,  G06F9/30145

Abstract: A system utilizes one or more programmable logic arrays or gate arrays for regulating the commands available to a microprocessor, and intercepting certain of those commands according to predetermined citeria. The system selects and processes designated commands relating to the FORCE-A20 signal and CPU-RESET signal for a keyboard controller functionally attached to an INTEL 80286 or 80386 microprocessor. The system includes one or more programmable logic arrays or gate arrays for allowing all input commands to pass directly through to the keyboard controller except the command sequence relating to the FORCE-A20 signal or the CPU-RESET signal.

Abstract translation: 系统利用一个或多个可编程逻辑阵列或门阵列来调节微处理器可用的命令，并根据预定的标准拦截某些命令。 系统选择并处理与INCE 80286或80386微处理器功能连接的键盘控制器的与FORCE-A20信号和CPU-RESET信号有关的指定命令。 该系统包括一个或多个可编程逻辑阵列或门阵列，用于允许所有输入命令直接通过键盘控制器，除了与FORCE-A20信号或CPU-RESET信号相关的命令序列。

公开(公告)号：US1859706A

公开(公告)日：1932-05-24

申请号：US48686630

申请日：1930-10-06

Applicant: GEN ANILINE WORKS INC

Inventor： WERNER LANGE

IPC: C09B43/10

CPC classification number: C09B43/10

公开(公告)号：US6148308A

公开(公告)日：2000-11-14

申请号：US55802

申请日：1993-04-30

Applicant: Edward J. Neubauer ,  Richard J. Gallaway ,  Juanita F. Bowden

Inventor： Edward J. Neubauer ,  Richard J. Gallaway ,  Juanita F. Bowden

IPC: G06F12/00 ,  G06F17/21 ,  G06F17/22 ,  G06F17/30

CPC classification number: G06F17/30595 ,  G06F17/212 ,  G06F17/22 ,  G06F17/2288 ,  Y10S707/954 ,  Y10S707/99954

Abstract: A method of selecting and representing time-varying data from a time-relational database management system by providing a unified view on a computer display screen. The data from a master record for a particular entity is displayed with a default video or character attribute, and is considered to be the current record. Accessing a history record for that entity causes the data for fields that differ from the corresponding fields of the current record to be overlaid on such current record fields but with a video or character attribute distinct from the default video or character attribute. The overlaid current record becomes a new current record for further overlays. Similarly, accessing a pending record causes the data for fields that differ from the corresponding fields of the current record to be overlaid on such current record fields but with a video or character attribute distinct from the default video or character attribute. A plurality of history or a plurality of pending records may be composited so that all of the changed fields for a set of records from the end of a defined time period can be overlaid on a current record at one time. Accessing an error record causes the data for fields that differ from the corresponding fields of the current record (current as of the date of the error record) to be overlaid on such current record fields but with a video or character attribute distinct from the default video or character attribute. Fields in the error record that are in error (whether changed or not from the current record data) are overlaid on the current record fields but with a video or character attribute distinct from both the default video or character attribute and the video or character attribute used to indicate changed fields in the error record.

Abstract translation: 一种通过在计算机显示屏幕上提供统一视图来从时间关系数据库管理系统中选择和表示时变数据的方法。 来自特定实体的主记录的数据以默认视频或字符属性显示，并被认为是当前记录。 访问该实体的历史记录导致与当前记录的相应字段不同的字段的数据被覆盖在当前记录字段上，但是具有与默认视频或字符属性不同的视频或字符属性。 覆盖的当前记录成为进一步叠加的新的当前记录。 类似地，访问挂起的记录导致与当前记录的相应字段不同的字段的数据被覆盖在这样的当前记录字段上，但是具有与默认视频或字符属性不同的视频或字符属性。 可以合成多个历史记录或多个待处理记录，使得从定义的时间段结束的一组记录的所有改变的字段可以一次叠加在当前记录上。 访问错误记录导致与当前记录的相应字段（截止错误记录日期的当前）不同的字段的数据覆盖在当前记录字段上，但视频或字符属性与默认视频不同 或字符属性。 错误记录中的错误记录（无论是否从当前记录数据更改）中的字段都覆盖在当前记录字段上，但与默认视频或字符属性以及所使用的视频或字符属性不同的视频或字符属性 以指示错误记录中的更改字段。

公开(公告)号：US6108763A

公开(公告)日：2000-08-22

申请号：US317411

申请日：1994-10-03

Applicant: Robert S. Grondalski

Inventor： Robert S. Grondalski

IPC: G06F11/10 ,  G06F15/80

CPC classification number: G06F11/10

Abstract: A processing array including a plurality of processing elements; and an interconnection network connected to all of the processing elements for carrying data messages between the processing elements, wherein each of the processing elements of the plurality of processing elements includes a parity generating circuit for generating a parity bit for a first data message that is transmitted by that processing element over the interconnection network to another processing element among the plurality of processing elements; and a parity checking circuit for checking parity of a second data message as it is received by that processing element over the the interconnection network, the parity checking and parity generating circuits being separate from each other and enabling that processing element to generate parity for the first data message being sent by that processing element while simultaneously checking parity of the second message received by that processing element.

Abstract translation: 一种包括多个处理元件的处理阵列; 以及连接到所有处理元件以用于在处理元件之间传送数据消息的互连网络，其中多个处理元件中的每个处理元件包括奇偶校验产生电路，用于产生被发送的第一数据消息的奇偶校验位 通过所述处理元件通过所述互连网络到所述多个处理元件中的另一处理元件; 以及奇偶校验电路，用于在通过所述互连网络由所述处理元件接收到的第二数据消息的奇偶校验中进行检查，所述奇偶校验和奇偶校验生成电路彼此分离，并且使得所述处理元件能够生成所述第一数据消息的奇偶校验 数据消息由该处理元件发送，同时检查由该处理元件接收到的第二消息的奇偶校验。