公开(公告)号：US08631177B1

公开(公告)日：2014-01-14

申请号：US12822956

申请日：2010-06-24

Applicant: Christopher Thomas

Inventor： Christopher Thomas

IPC: G06F13/00 ,  G06F3/00

CPC classification number: G06F3/0632 ,  G06F3/0607 ,  G06F3/0673 ,  G06F13/426

Abstract: Various techniques are provided for hosting storage media devices using multi-port devices having a plurality of ports. For example, in one embodiment, a method of operating a multi-port device includes detecting whether a host device or a storage media device is connected to a first port of the multi-port device or a second port of the multi-port device. The method also includes, if the host device is connected to the first port, configuring the first port as a slave port and operating the multi-port device as a slave hosted by the host device. The method also includes, if the host device is connected to the second port and the storage media device is connected to the first port, configuring the first port as a host port and hosting the storage media device from the multi-port device.

Abstract translation: 提供了使用具有多个端口的多端口设备来托管存储介质设备的各种技术。 例如，在一个实施例中，操作多端口设备的方法包括检测主机设备或存储介质设备是否连接到多端口设备的第一端口或多端口设备的第二端口。 该方法还包括如果主机设备连接到第一端口，则将第一端口配置为从端口，并将多端口设备作为由主机设备托管的从设备进行操作。 该方法还包括如果主机设备连接到第二端口并且存储介质设备连接到第一端口，则将第一端口配置为主机端口并且从多端口设备托管存储介质设备。

公开(公告)号：US08575973B1

公开(公告)日：2013-11-05

申请号：US13481038

申请日：2012-05-25

Applicant: Xianyao Wang ,  Peter E. Sheldon ,  Christopher M. Green

Inventor： Xianyao Wang ,  Peter E. Sheldon ,  Christopher M. Green

IPC: H03B21/00

CPC classification number: H03B21/00 ,  G06F1/022 ,  H03B2202/02

Abstract: A frequency synthesizer system may generate two intermediate clock signals, each intermediate clock signal having the same nominal frequency (fN), the same cycle pattern with deterministic jitter, and the same corresponding average frequency (fA). However, the cycle pattern in one intermediate clock signal may be a specified number (N) of cycles out of phase with respect to the cycle pattern in the other intermediate clock signal. The cycle pattern may recur every 2N cycles in each intermediate clock signal. The duration of each cycle in each of the two intermediate clock signals is defined by fN and the deterministic jitter in the cycle pattern. An output clock signal may be generated by phase interpolating by two (2) the two intermediate clock signals, and dividing the resulting phase interpolated clock signal by N. The resulting output clock signal has an accurate frequency commensurate with fA/N, and is free of deterministic jitter.

Abstract translation: 频率合成器系统可以产生两个中间时钟信号，每个中间时钟信号具有相同的标称频率（fN），具有确定性抖动的相同周期模式和相同的相应平均频率（fA）。 然而，一个中间时钟信号中的周期模式可以是相对于另一个中间时钟信号中的周期模式的异相的指定数量（N）个周期。 在每个中间时钟信号中，循环模式可以每2N个循环重复。 两个中间时钟信号中每一个周期的持续时间由fN和循环模式中的确定性抖动来定义。 可以通过两（2）个中间时​​钟信号进行相位内插来产生输出时钟信号，并将得到的相位内插时钟信号除以N.由此产生的输出时钟信号具有与fA / N相当的精确频率，并且是空闲的 的确定性抖动。

公开(公告)号：US08516290B1

公开(公告)日：2013-08-20

申请号：US12698752

申请日：2010-02-02

Applicant: Christopher Thomas

Inventor： Christopher Thomas

IPC: G06F13/42 ,  G06F13/14 ,  G06F13/36

CPC classification number: G06F13/405

Abstract: Various techniques are provided for bridging interfaces, such as different interfaces for use with a host device. In one example, a system includes an asynchronous first interface adapted to transmit and receive data to and from a host device in accordance with a first protocol. A synchronous second interface is adapted to transmit and receive data to and from a device external to the host device in accordance with a second protocol. A bridge controller is adapted to convert the data received from the host device from the first protocol to the second protocol for transmission to the external device. A clock and data recovery (CDR) block is adapted to recover a clock signal from the first interface to synchronize the data received from the host device. The second interface is adapted to synchronize the converted second protocol data transmitted to the external device using the recovered clock signal.

Abstract translation: 提供各种技术用于桥接接口，例如用于主机设备的不同接口。 在一个示例中，系统包括适于根据第一协议向主机设备发送数据和从主机设备接收数据的异步第一接口。 同步第二接口适于根据第二协议向主设备外部的设备发送数据和从主设备外部的设备接收数据。 桥接控制器适于将从主机设备接收的数据从第一协议转换为第二协议以传输到外部设备。 时钟和数据恢复（CDR）块适于从第一接口恢复时钟信号以使从主机设备接收的数据同步。 第二接口适于使用恢复的时钟信号来同步发送到外部设备的转换的第二协议数据。

公开(公告)号：US08391420B1

公开(公告)日：2013-03-05

申请号：US12721365

申请日：2010-03-10

Applicant: Hongming An ,  Wei Fu ,  CongQing Xiong ,  James Ho

Inventor： Hongming An ,  Wei Fu ,  CongQing Xiong ,  James Ho

IPC: H04L27/00 ,  H04L27/10 ,  H02P11/00

CPC classification number: H04L25/0272 ,  H04L25/0292

Abstract: Various techniques are provided to detect a state of a communication signal. In one example, a method of detecting a state of a signal includes receiving a differential communication signal comprising a positive portion and a complementary negative portion. The method also includes filtering the positive portion of the communication signal through a first low pass filter to provide a filtered positive portion of the communication signal. The method also includes filtering the negative portion of the communication signal through a second low pass filter to provide a filtered negative portion of the communication signal. The method also includes comparing the filtered positive portion of the communication signal with an internal reference voltage. The method also includes comparing the filtered negative portion of the communication signal with the internal reference voltage. The method also includes generating a low frequency detect signal in response to the comparing operations to indicate whether the communication signal is in a low frequency state.

Abstract translation: 提供各种技术来检测通信信号的状态。 在一个示例中，检测信号状态的方法包括接收包括正部分和互补负部分的差分通信信号。 该方法还包括通过第一低通滤波器对通信信号的正部分进行滤波，以提供经过滤波的通信信号的正部分。 该方法还包括通过第二低通滤波器对通信信号的负部分进行滤波，以提供经过滤波的通信信号的负部分。 该方法还包括将通信信号的经滤波的正部分与内参考电压进行比较。 该方法还包括将通信信号的滤波后的负部分与内部基准电压进行比较。 该方法还包括响应于比较操作产生低频检测信号，以指示通信信号是否处于低频状态。

公开(公告)号：US08384485B2

公开(公告)日：2013-02-26

申请号：US13097671

申请日：2011-04-29

Applicant: Justin L. Fortier ,  Ralph D. Mason

Inventor： Justin L. Fortier ,  Ralph D. Mason

IPC: H03L7/001

CPC classification number: H03L5/00 ,  H03L7/099 ,  H03L7/24 ,  H04B17/11

Abstract: Various embodiments of a radio-frequency (RF) transmitter receiver circuit that utilizes an injection locked oscillator may allow for the introduction of a DC offset to correct the RF signal. The DC offset may be adjusted to eliminate (or minimize) even order harmonics to correct for RF effects. The DC offset correction may be performed around the injection locked oscillator to target even order terms.

Abstract translation: 使用注入锁定振荡器的射频（RF）发射器接收器电路的各种实施例可以允许引入DC偏移来校正RF信号。 可以调整DC偏移以消除（或最小化）偶次谐波以校正RF效应。 可以在注入锁定振荡器周围执行DC偏移校正，以达到偶数阶。

公开(公告)号：US08351559B1

公开(公告)日：2013-01-08

申请号：US12759574

申请日：2010-04-13

Applicant: Christopher Thomas

Inventor： Christopher Thomas

IPC: H04L7/00

CPC classification number: H04L7/0337 ,  H03L7/00

Abstract: Systems and methods are provided to permit indirect measurements of sample time errors using multiphase interpolator clocks generated from a local reference clock in clock recovery blocks of high speed data receivers. The multiphase interpolator clocks are adjusted to have substantially evenly spaced phase offsets within a data period of the local reference clock. A small frequency offset between the transmitter clock and the local reference clock causes transition edges of received data to drift slowly across the interpolated clocks. Differences in phase offsets between the interpolated clocks may be determined with high resolution by counting the number of data transitions occurring between pairs of interpolated clocks over a long period of time. Phase offsets are adjusted to make the data transition counts substantially the same for the interpolated clocks. Data recovery may then be facilitated by selecting an interpolated clock with a sampling edge that is closest to the center of a data period to sample the received data.

Abstract translation: 提供了系统和方法，以使用从高速数据接收器的时钟恢复块中的本地参考时钟产生的多相内插器时钟来间接测量采样时间误差。 调整多相内插器时钟以在本地参考时钟的数据周期内具有基本上均匀间隔的相位偏移。 发射机时钟和本地参考时钟之间的小的频率偏移导致接收的数据的转换边缘在内插时钟上缓慢漂移。 内插时钟之间的相位偏移的差异可以通过在长时间段内对内插时钟对之间发生的数据转换的数量进行计数，以高分辨率来确定。 调整相位偏移，使内插时钟的数据转换计数基本相同。 然后可以通过选择具有最接近数据周期的中心的采样边缘的内插时钟来对接收的数据进行采样来促进数据恢复。

公开(公告)号：US08291125B2

公开(公告)日：2012-10-16

申请号：US13028762

申请日：2011-02-16

Applicant: Gideon David Intrater ,  Biao Jia ,  Teck Huat Kerk ,  Qing Yun Li

Inventor： Gideon David Intrater ,  Biao Jia ,  Teck Huat Kerk ,  Qing Yun Li

IPC: G06F3/00

CPC classification number: G06F13/102 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679

Abstract: Systems and methods for a mass storage device attached to a host device use speculation about the host command likely to be received next from the host device based on a previously received command to improve throughput of accesses to the mass storage device. Host commands are used to speculatively produce commands for data storage devices of the mass storage device, such that host commands speculated as being likely next can be started during idle time of the data storage devices, based upon the probability that the speculation will be correct some of the time, and otherwise wasted idle time will be more efficiently used. Time taken by the host device to produce successive commands to the mass storage system is monitored, and future speculatively produced commands are parameterized to complete within the observed host time to produce new commands, making more efficient use of the data storage devices.

Abstract translation: 用于连接到主机设备的大容量存储设备的系统和方法基于先前接收到的用于提高对大容量存储设备的访问的吞吐量的命令，使用关于主机设备可能接收的主机命令的推测。 主机命令用于推测地为大容量存储设备的数据存储设备产生命令，使得可以在数据存储设备的空闲时间期间推测出可能接下来的主机命令可以基于投机将是正确的可能性 的时间，否则浪费的空闲时间将更有效地使用。 监视主机设备向大容量存储系统产生连续命令所用的时间，并且将来的推测产生的命令被参数化以在所观察的主机时间内完成以产生新的命令，从而更有效地使用数据存储设备。

公开(公告)号：US20120201126A1

公开(公告)日：2012-08-09

申请号：US13451908

申请日：2012-04-20

Applicant: David J. Knapp

Inventor： David J. Knapp

IPC: H04L12/28 ,  H04L12/56 ,  H04L12/26

CPC classification number: H04L12/437 ,  H04L12/43 ,  H04L45/28 ,  H04L2012/40273

Abstract: A data communication system and an associated network node implementation is disclosed that, in certain embodiments, uses single-channel bi-directional communication links between nodes to send frames of data. The network nodes can be connected together in a ring or daisy chain topology with data frames sent in alternating directions through the bi-directional links. Such networks initially configured in a physical ring topology can tolerate single point failures by automatically switching to a logical daisy chain topology.

Abstract translation: 公开了一种数据通信系统和相关联的网络节点实现，其在某些实施例中使用节点之间的单信道双向通信链路来发送数据帧。 网络节点可以通过双向链路以交替方向发送的数据帧以环形或菊花链拓扑连接在一起。 最初配置在物理环形拓扑中的这种网络可以通过自动切换到逻辑菊花链拓扑来容忍单点故障。

公开(公告)号：US09141780B2

公开(公告)日：2015-09-22

申请号：US13301809

申请日：2011-11-22

Applicant: Ramanathan Subramaniam ,  Hooman Kashef Hamadani

Inventor： Ramanathan Subramaniam ,  Hooman Kashef Hamadani

IPC: G06F7/04 ,  G06F15/16 ,  G06F17/30 ,  H04L29/06 ,  G06F21/33 ,  G06F21/44

CPC classification number: G06F21/33 ,  G06F21/445 ,  G06F2221/2103

Abstract: Embodiments of the present disclosure provide a method and system for authenticating communication between a plurality of accessory devices or services and one or more media devices by using a single authentication processor. The method includes the steps of establishing a communication of a media device attached to an accessory device with an authentication processor through an authentication processor manager, authenticating the accessory device by the media device based on a digital certificate and a digital signature; and authenticating the media device by the accessory device based on verification of the digital certificate and the digital signature.

Abstract translation: 本公开的实施例提供了一种用于通过使用单个认证处理器来认证多个附件设备或服务与一个或多个媒体设备之间的通信的方法和系统。 该方法包括以下步骤：通过认证处理器管理器建立与附件设备相连的媒体设备与认证处理器的通信，由媒体设备基于数字证书和数字签名验证附件设备; 以及基于数字证书和数字签名的验证，通过附件设备认证媒体设备。

公开(公告)号：US08935557B2

公开(公告)日：2015-01-13

申请号：US13407153

申请日：2012-02-28

Applicant: Timothy J. Knowlton ,  Miroslav Oljaca

Inventor： Timothy J. Knowlton ,  Miroslav Oljaca

IPC: G06F1/26

CPC classification number: G06F1/266 ,  G06F1/263

Abstract: A port power switch (PPS) may be used for lead compensation in systems where power is provided to a connected device by a switch-mode power supply (SMPS). The PPS may be designed to co-operate with the SMPS, providing a mechanism for the feedback reference point of the SMPS to be automatically switched, in the event of system fault or some other condition that might result in the PPS entering an “OFF’ operating mode, from the application point of load (POL) to the voltage input pin of the PPS without loss of power path continuity. The switching mechanism and the PPS may be manufactured to reside on the same integrated circuit. The PPS may include a control block that generates a control signal to couple the feedback port of the SMPS to the POL under normal operation, and to the voltage input port of the PPS during a fault condition.

Abstract translation: 在通过开关电源（SMPS）向连接的设备供电的系统中，端口电源开关（PPS）可用于引线补偿。 PPS可以被设计为与SMPS协作，在系统故障或可能导致PPS进入“OFF”（关））的情况下，提供用于SMPS的反馈参考点自动切换的机制， 工作模式，从负载（POL）的应用点到PPS的电压输入引脚，而不损失电源通路的连续性。 开关机构和PPS可以制造在同一集成电路上。 PPS可以包括控制块，其在正常操作期间产生控制信号以将SMPS的反馈端口连接到POL，以及在故障状态期间产生PPS的电压输入端口。