公开(公告)号：US20010028353A1

公开(公告)日：2001-10-11

申请号：US09825926

申请日：2001-04-05

发明人： Nai-Sheng Cheng

IPC分类号： G06F013/14 ,  G09G005/39 ,  G06F012/00

CPC分类号： G06F5/10 ,  G06F3/14 ,  G06F2205/108

摘要： A method and a system for buffer management is provided. The system includes a central processing unit, a multimedia chip, a buffer, a beginning register, an ending register, and a pause register. The beginning register is employed to store a beginning address of the buffer, and the ending register is used to storing an ending address of the buffer or buffer length. Content of the pause register is a data address associated with a command data. In addition, the pause register includes a pause code. When the pause code is equal to a first value, after the multimedia chip reads command data associated with the content of the pause register, reading is stopped, and the command data next to the command data are to be read in the next reading. When the pause code is equal to a second value, after the multimedia chip reads the command data associated with the content of the pause register, the multimedia chip continues to reads command data associated with the beginning register.

摘要翻译： 提供了缓冲区管理的方法和系统。 该系统包括中央处理单元，多媒体芯片，缓冲器，起始寄存器，结束寄存器和暂停寄存器。 采用开始寄存器来存储缓冲区的起始地址，结束寄存器用于存储缓冲区或缓冲区长度的结束地址。 暂停寄存器的内容是与命令数据相关联的数据地址。 此外，暂停寄存器包括暂停码。 当暂停码等于第一值时，在多媒体芯片读取与暂停寄存器的内容相关联的命令数据之后，停止读取，并且在下一个读取中读取与命令数据相邻的命令数据。 当暂停码等于第二值时，在多媒体芯片读取与暂停寄存器的内容相关联的命令数据之后，多媒体芯片继续读取与起始寄存器相关联的命令数据。

公开(公告)号：US06208566B1

公开(公告)日：2001-03-27

申请号：US09261118

申请日：1999-03-03

申请人： Osamu Kuroki ,  Masakuni Kawagoe

发明人： Osamu Kuroki ,  Masakuni Kawagoe

IPC分类号： G11C700

CPC分类号： G06F5/10 ,  G06F2205/108

摘要： A first data store circuit is coupled to first and second voltage nodes of first and second voltage levels, respectively, and a control circuit outputs a transfer signal and a switching signal. A data transfer circuit is coupled between the first data store circuit and a second data store circuit and selectively transfers the data in the first data store circuit to the second data store circuit in response to the transfer signal. A first conductive line supplies the first voltage level to the second data store circuit and a second conductive line supplies the second voltage level to the second data store circuit. A first switch circuit is coupled between the second voltage node and the second conductive line and selectively connects the second voltage node to the second conductive line in response to the switching signal. Also a resistive element is coupled between the second conductive line and the first voltage node.

摘要翻译： 第一数据存储电路分别耦合到第一和第二电压电平的第一和第二电压节点，并且控制电路输出传输信号和开关信号。 数据传输电路耦合在第一数据存储电路和第二数据存储电路之间，并响应于传送信号选择性地将第一数据存储电路中的数据传送到第二数据存储电路。 第一导线将第一电压电平提供给第二数据存储电路，第二导线将第二电压电平提供给第二数据存储电路。 第一开关电路耦合在第二电压节点和第二导线之间，并且响应于开关信号选择性地将第二电压节点连接到第二导线。 电阻元件还耦合在第二导线和第一电压节点之间。

公开(公告)号：US5379399A

公开(公告)日：1995-01-03

申请号：US880440

申请日：1992-05-08

申请人： David C. Conway-Jones ,  Peter M. Smith

发明人： David C. Conway-Jones ,  Peter M. Smith

IPC分类号： G06F13/38 ,  G06F5/10 ,  G06F5/12 ,  G06F13/28 ,  G11C7/00 ,  H04N5/907 ,  G06F13/00

CPC分类号： G06F5/10 ,  G06F13/28 ,  G06F2205/108

摘要： A controller for a first in first out (FIFO) memory comprises detector logic for detecting any difference between the number of addresses in the memory into which data is written and the number of addresses in the memory from which data is read. Comparator logic connected to the detector logic generates a request data transfer signal in response to said difference becoming greater than or equal to a threshold. Threshold select logic connected to the comparator logic is responsive to data having first and second portions being written to the memory. The threshold select logic sets the threshold to a first value when the first portion is being written and sets the threshold to a second value, greater than the first value, when the second portion is being written. Because different thresholds are assoicated with the portions, data, such as a digitized video signal having active line portions separated by control portions for example, can be transferred via the FIFO from one system to another more efficiently in terms of communication bandwidth usage.

摘要翻译： 用于先进先出（FIFO）存储器的控制器包括用于检测写入数据的存储器中的地址数与读取数据的存储器中的地址数之间的任何差异的检测器逻辑。 连接到检测器逻辑的比较器逻辑响应于所述差变大于或等于阈值而产生请求数据传送信号。 连接到比较器逻辑的阈值选择逻辑响应于具有被写入存储器的第一和第二部分的数据。 当第一部分被写入时，阈值选择逻辑将阈值设置为第一值，并且当第二部分被写入时将阈值设置为大于第一值的第二值。 由于不同的阈值与部分有关，所以在通信带宽使用方面，诸如具有由例如控制部分隔开的有效行部分的数字化视频信号的数据可以经由FIFO从一个系统传送到另一个系统。

公开(公告)号：US4916658A

公开(公告)日：1990-04-10

申请号：US135170

申请日：1987-12-18

申请人： Chien-Chyun Lee ,  Charles R. Moore

发明人： Chien-Chyun Lee ,  Charles R. Moore

IPC分类号： G06F9/38 ,  G06F5/06 ,  G06F5/10 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F5/10 ,  G06F2205/108

摘要： A buffer for storing data words consisting of several storage locations together with circuitry providing a first indicator that designates the next storage location to be stored into, a second indicator designating the next storage location to be retrieved from, and circuitry that provides the number of locations available for storage and the number of locations available for retrieval. Furthermore, the buffer includes the capability to store and retrieve several data words simultaneously.

公开(公告)号：US08099546B2

公开(公告)日：2012-01-17

申请号：US12481397

申请日：2009-06-09

申请人： Steven D. Rostedt

发明人： Steven D. Rostedt

IPC分类号： G06F12/00

CPC分类号： G06F9/52 ,  G06F5/10 ,  G06F11/3636 ,  G06F2205/064 ,  G06F2205/108

摘要： In one embodiment, a mechanism for a lockless ring buffer in overwrite mode is disclosed. In one embodiment, a method for implementing a lockless ring buffer in overwrite mode includes aligning memory addresses for each page of a ring buffer to form maskable bits in the address to be used as a state flag for the page and utilizing at least a two least significant bits of each of the addresses to represent the state flag associated with the page represented by the address, wherein the state flag indicates one of three states including a header state, an update state, and a normal state. The method further includes combining a movement of a head page pointer to a head page of the ring buffer with a swapping of the head page and a reader page, the combining comprising updating the state flag of the head page pointer to the normal state and updating the state flag of a pointer to the page after the head page to the header state, and moving the head page and a tail page of the ring buffer, the moving comprising updating the state flags of one or more pointers in the ring buffer associated with the head page and the tail page.

摘要翻译： 在一个实施例中，公开了一种用于重写模式下的无锁环缓冲器的机构。 在一个实施例中，一种用于在重写模式下实现无锁环缓冲器的方法包括：对于环形缓冲器的每个页面的存储器地址进行对齐，以形成地址中的可屏蔽位，以用作页面的状态标志，并且利用至少两个最小 每个地址的有效位表示与由地址表示的页相关联的状态标志，其中状态标志指示包括报头状态，更新状态和正常状态的三种状态之一。 该方法还包括将首页指针与环形缓冲器的头部页面的移动与头部页面和读取器页面的交换相结合，该组合包括将头部页面指针的状态标志更新为正常状态并更新 在首页到头部状态之后的指向页面的指针的状态标志，以及移动环形缓冲器的头部页面和尾页，移动包括更新与相关联的环形缓冲器中的一个或多个指针的状态标志 首页和尾页。

公开(公告)号：US20110276731A1

公开(公告)日：2011-11-10

申请号：US13185255

申请日：2011-07-18

申请人： Heyun Howard Liu

发明人： Heyun Howard Liu

IPC分类号： G06F5/14

CPC分类号： G06F5/12 ,  G06F5/10 ,  G06F2205/108 ,  G06F2205/123 ,  H04L49/90 ,  H04L49/9089

摘要： A network node (5) including a line card (20) for packet-based data communications is disclosed. The line card (20) includes a transmit FIFO buffer (24T) and a receive FIFO buffer (24R), for buffering communications within the line card (20). Each of the buffers (24T, 24R) operate in a dual-port fashion, receiving asynchronous read and write requests, for reading data words from and writing data words to the buffers (24T, 24R). The buffers (24T, 24R) each include a memory array (45) of conventional single port random access memory cells, for example static RAM cells. Clock cycles are assigned by the buffers (24T, 24R) as internal read and internal write cycles, in alternating fashion. A write buffer (42) receives input data words, and schedules a double-data-word write to the memory array (45) upon receiving a pair of input data words, in the next internal write cycle. A read request buffer (44) receives read strobes, or read enable signals, from a downstream function, and upon receiving two such strobes, schedules the read of a double-data-word from the memory array (45). By converting the asynchronous read and write requests into scheduled reads and writes, respectively, the buffers (24T, 24R) operate as dual-port FIFO buffers.

摘要翻译： 公开了一种包括用于基于分组的数据通信的线路卡（20）的网络节点（5）。 线卡（20）包括发送FIFO缓冲器（24T）和接收FIFO缓冲器（24R），用于缓冲线卡（20）内的通信。 每个缓冲器（24T，24R）以双端口方式工作，接收异步读和写请求，用于从缓冲器（24T，24R）读取数据字并将数据字写入缓冲器（24T，24R）。 缓冲器（24T，24R）各自包括常规单端口随机存取存储器单元的存储器阵列（45），例如静态RAM单元。 时钟周期由缓冲器（24T，24R）分配为内部读和内部写周期，以交替方式。 写入缓冲器（42）接收输入数据字，并且在下一个内部写周期中接收到一对输入数据字后，对存储器阵列（45）进行双数据字写入。 读取请求缓冲器（44）从下游功能接收读取选通信号或读取使能信号，并且在接收到两个这样的选通信号时，从存储器阵列（45）调度双数据字的读取。 通过将异步读取和写入请求分别转换为预定的读取和写入，缓冲器（24T，24R）作为双端口FIFO缓冲器运行。

公开(公告)号：US20100312975A1

公开(公告)日：2010-12-09

申请号：US12481376

申请日：2009-06-09

申请人： Steven D. Rostedt

发明人： Steven D. Rostedt

IPC分类号： G06F12/00 ,  G06F9/44

CPC分类号： G06F11/3636 ,  G06F5/10 ,  G06F11/3648 ,  G06F2205/064 ,  G06F2205/108

摘要： In one embodiment, a mechanism for a reader page for a ring buffer is disclosed. In one embodiment, a method for implementing a reader page for a ring buffer includes allocating, by a processing device, a block of storage separate from a ring buffer as a reader page for a reader of the ring buffer, the ring buffer stored in a physical memory device, and swapping, by the processing device, a head page of the ring buffer with the reader page so that the reader page is part of the ring buffer and the head page is no longer attached to the ring buffer.

摘要翻译： 在一个实施例中，公开了一种用于环形缓冲器的读取器页面的机构。 在一个实施例中，用于实现环形缓冲器的读取器页面的方法包括：通过处理设备将与环形缓冲区分开的存储块分配为环形缓冲器的读取器的读取器页面，存储在环形缓冲器中的环形缓冲器 物理存储设备，并且由处理设备交换具有读取器页面的环形缓冲器的头页，使得读取器页面是环形缓冲器的一部分，并且头部页面不再附着到环形缓冲器。

公开(公告)号：US07805552B2

公开(公告)日：2010-09-28

申请号：US11040896

申请日：2005-01-21

申请人： Mario Au ,  Jason Z. Mo ,  Hui Su

发明人： Mario Au ,  Jason Z. Mo ,  Hui Su

IPC分类号： G06F13/00 ,  G06F3/00 ,  G06F5/00

CPC分类号： G06F5/065 ,  G06F2205/108

摘要： A multi-queue memory system is configured to operate in a packet mode. Each packet includes a SOP (start of packet) marker and an EOP (end of packet) marker. A packet status bit (PSB), is used to implement the packet mode. The packet status bit enables partial packet write and partial packet read operations, such that a queue switch can be performed in the middle of packet write or packet read operations. The packet status bit also enables data filtering to be performed between an activated EOP marker and a subsequently received SOP marker (i.e., between the end of one packet and the start of the next packet). Packet mark and re-write and packet mark and re-read operations are also enabled.

摘要翻译： 多队列存储器系统被配置为以分组模式操作。 每个分组包括SOP（分组开始）标记和EOP（分组结束）标记。 分组状态位（PSB）用于实现分组模式。 分组状态位使得能够进行部分分组写入和部分分组读取操作，使得可以在分组写入或分组读取操作的中间执行队列切换。 分组状态位还使得能够在激活的EOP标记和随后接收的SOP标记（即，在一个分组的结束和下一个分组的开始之间）之间执行数据过滤。 数据包标记和重写以及数据包标记和重新读取操作也被启用。

公开(公告)号：US20100088424A1

公开(公告)日：2010-04-08

申请号：US12245779

申请日：2008-10-06

申请人： Gidon Gershinsky ,  Konstantin Shagin

发明人： Gidon Gershinsky ,  Konstantin Shagin

IPC分类号： G06F15/173

CPC分类号： G06F5/14 ,  G06F2205/063 ,  G06F2205/108

摘要： Buffering messages by receiving a message from a messaging client, writing the message to a logically-contiguous write-available region of a message buffer starting at a logically next write-available location within the write-available region, updating a head index to indicate a head boundary between a logically last message in the message buffer and a logically next write-available location in the message buffer, defining a packet including the message within the message buffer, transmitting a packet that includes a logically first message in the message buffer, and updating a tail index to indicate a tail boundary between a new logically last write-available location in the message buffer and a new logically first message in the message buffer.

摘要翻译： 通过从消息传递客户端接收消息来缓冲消息，将消息写入消息缓冲器的逻辑上连续的写可用区域，从写可用区域内的逻辑下一个写可用位置开始，更新头索引以指示 在消息缓冲器中的逻辑上一个消息与消息缓冲器中的逻辑下一个写可用位置之间的头部边界，定义包含消息缓冲器内的消息的分组，在消息缓冲器中发送包括逻辑上第一消息的分组，以及 更新尾部索引以指示消息缓冲器中新的逻辑上一个可写入可用位置与消息缓冲器中新的逻辑上第一个消息之间的尾部边界。

公开(公告)号：US07421459B2

公开(公告)日：2008-09-02

申请号：US10091778

申请日：2002-03-06

申请人： Robin Alexis Takasugi ,  Stewart R. Wyatt

发明人： Robin Alexis Takasugi ,  Stewart R. Wyatt

IPC分类号： G06F17/30

CPC分类号： G06F5/14 ,  G06F2205/108 ,  Y10S707/99955

摘要： Systems and methods for transferring data between a host device and a storage medium are provided. In one implementation, a system for transferring data between a host device and a storage medium includes a host interface that receives from the host device a command to transfer data between the host device and the storage medium, a buffer that temporarily stores data that is transferred between the host device and the storage medium, a first register that stores a value for tracking a number of data units that have been transferred into the buffer but that have not yet been transferred out of the buffer, a second register that stores a value for incrementing a value contained in the first register, and a third register that stores a value for decrementing a value contained in the first register.

摘要翻译： 提供了用于在主机设备和存储介质之间传送数据的系统和方法。 在一个实现中，用于在主机设备和存储介质之间传送数据的系统包括主机接口，主机接口从主机设备接收在主设备和存储介质之间传送数据的命令，临时存储传输的数据的缓冲器 在所述主机设备和所述存储介质之间存储第一寄存器，所述第一寄存器存储用于跟踪已经被传送到所述缓冲器中但尚未被传送到所述缓冲器的数据单元的数量的值;第二寄存器， 增加包含在第一寄存器中的值，以及第三寄存器，其存储用于递减包含在第一寄存器中的值的值。