公开(公告)号：US08139305B2

公开(公告)日：2012-03-20

申请号：US12558928

申请日：2009-09-14

申请人： George Mathew ,  Hongwei Song ,  Yuan Xing Lee

发明人： George Mathew ,  Hongwei Song ,  Yuan Xing Lee

IPC分类号： G11B5/35

CPC分类号： G11B20/10009 ,  G11B20/10027 ,  G11B20/10222 ,  G11B20/10435 ,  G11B20/1049 ,  G11B2220/2516

摘要： Various embodiments of the present invention provide systems and methods for acquiring timing and/or gain information. For example, various embodiments of the present invention provide data processing circuits that include a sample splitting circuit, a first averaging circuit, a second averaging circuit and a parameter calculation circuit. The sample splitting circuit receives a data input that includes a series of samples that repeat periodically over at least a first phase and a second phase. The sample splitting circuit divides the series of samples into at least a first sub-stream corresponding to the first phase and a second sub-stream corresponding to the second phase. The first averaging circuit averages values from the first sub-stream to yield a first average, and the second averaging circuit averages values from the second sub-stream to yield a second average. The parameter calculation circuit calculates a parameter value based at least in part on the first average and the second average.

摘要翻译： 本发明的各种实施例提供了用于获取定时和/或增益信息的系统和方法。 例如，本发明的各种实施例提供了包括采样分离电路，第一平均电路，第二平均电路和参数计算电路的数据处理电路。 采样分离电路接收包括在至少第一阶段和第二阶段周期性地重复的一系列样本的数据输入。 样本分割电路将该系列样本划分成对应于第一相的至少第一子流和对应于第二相的第二子流。 第一平均电路平均来自第一子流的值以产生第一平均值，并且第二平均电路平均来自第二子流的值以产生第二平均值。 参数计算电路至少部分地基于第一平均值和第二平均值来计算参数值。

公开(公告)号：US20110063747A1

公开(公告)日：2011-03-17

申请号：US12558928

申请日：2009-09-14

申请人： George Mathew ,  Hongwei Song ,  Yuan Xing Lee

发明人： George Mathew ,  Hongwei Song ,  Yuan Xing Lee

IPC分类号： G11B20/10

CPC分类号： G11B20/10009 ,  G11B20/10027 ,  G11B20/10222 ,  G11B20/10435 ,  G11B20/1049 ,  G11B2220/2516

摘要： Various embodiments of the present invention provide systems and methods for acquiring timing and/or gain information. For example, various embodiments of the present invention provide data processing circuits that include a sample splitting circuit, a first averaging circuit, a second averaging circuit and a parameter calculation circuit. The sample splitting circuit receives a data input that includes a series of samples that repeat periodically over at least a first phase and a second phase. The sample splitting circuit divides the series of samples into at least a first sub-stream corresponding to the first phase and a second sub-stream corresponding to the second phase. The first averaging circuit averages values from the first sub-stream to yield a first average, and the second averaging circuit averages values from the second sub-stream to yield a second average. The parameter calculation circuit calculates a parameter value based at least in part on the first average and the second average.

摘要翻译： 本发明的各种实施例提供了用于获取定时和/或增益信息的系统和方法。 例如，本发明的各种实施例提供了包括采样分离电路，第一平均电路，第二平均电路和参数计算电路的数据处理电路。 采样分离电路接收包括在至少第一阶段和第二阶段周期性地重复的一系列样本的数据输入。 样本分割电路将该系列样本划分成对应于第一相的至少第一子流和对应于第二相的第二子流。 第一平均电路平均来自第一子流的值以产生第一平均值，并且第二平均电路平均来自第二子流的值以产生第二平均值。 参数计算电路至少部分地基于第一平均值和第二平均值来计算参数值。

公开(公告)号：US08693120B2

公开(公告)日：2014-04-08

申请号：US13050765

申请日：2011-03-17

申请人： Shaohua Yang ,  Changyou Xu ,  Wu Chang ,  Ming Jin

发明人： Shaohua Yang ,  Changyou Xu ,  Wu Chang ,  Ming Jin

IPC分类号： G11B5/09

CPC分类号： G11B20/1217 ,  G11B20/10435 ,  G11B20/10462 ,  G11B20/1403 ,  G11B2020/1284 ,  G11B2020/1476 ,  G11B2220/2516

摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a read circuit and a combining circuit. The read circuit is operable to provide a first instance of a user data set, a second instance of the user data set, and a third instance of the user data set. The combining circuit is operable to: combine at least a first segment of the first instance of the user data set with a first segment of the second instance of the user data set to yield a first combined data segment; provide a second combined data set that includes a combination of one or more second segments from the second instance of the user data set and the third instance of the user data set; and provide an aggregate data set including at least the first combined data set and the second combined data set. The second combined data set does not incorporate a second segment of the first instance of the user data set.

摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例，公开了包括读取电路和组合电路的数据处理电路。 读取电路可操作以提供用户数据集的第一实例，用户数据集的第二实例以及用户数据集的第三实例。 组合电路可操作为：将用户数据集的第一实例的至少第一段与用户数据集的第二实例的第一段组合以产生第一组合数据段; 提供第二组合数据集，其包括来自用户数据集的第二实例和用户数据集的第三实例的一个或多个第二段的组合; 并提供包括至少第一组合数据集和第二组合数据集的聚合数据集。 第二组合数据集不包括用户数据集的第一实例的第二段。

公开(公告)号：US08687301B1

公开(公告)日：2014-04-01

申请号：US13736804

申请日：2013-01-08

申请人： LSI Corporation

发明人： Fan Zhang ,  Jun Xiao ,  Haitao Xia

IPC分类号： G11B20/10

CPC分类号： G11B20/1403 ,  G11B20/10268 ,  G11B20/10435 ,  G11B2020/1287

摘要： The disclosure is directed to detection of a sync mark location for at least one data sector of a disk by processing a first sector and at least a second sector in parallel. A first set of data samples from the first sector is reframed according to one or more sync mark locations based upon a first selected sync mark location, and a second set of data samples from the second sector is reframed according to one or more sync mark locations based upon a second selected sync mark location. The first set of data samples and the second set of data samples are iteratively reframed and decoded until the first sector or the second sector converges or until all possible sync mark locations have been attempted.

摘要翻译： 本公开涉及通过并行处理第一扇区和至少第二扇区来检测盘的至少一个数据扇区的同步标记位置。 基于第一选择的同步标记位置，根据一个或多个同步标记位置来重新编码来自第一扇区的第一组数据样本，并且根据一个或多个同步标记位置重新构造来自第二扇区的第二组数据采样 基于第二选择的同步标记位置。 第一组数据样本和第二组数据样本被迭代地重构和解码，直到第一扇区或第二扇区收敛或直到尝试所有可能的同步标记位置为止。

公开(公告)号：US08599663B1

公开(公告)日：2013-12-03

申请号：US12247009

申请日：2008-10-07

申请人： Tom Geukens

发明人： Tom Geukens

IPC分类号： G11B17/00 ,  G11B7/00 ,  G11B27/36 ,  G11B20/18 ,  G11B5/09 ,  G11B20/14

CPC分类号： G11B7/00 ,  G11B7/00456 ,  G11B7/1263 ,  G11B20/10027 ,  G11B20/10435 ,  G11B20/14 ,  G11B20/1426 ,  G11B20/18 ,  G11B2220/2537

摘要： An approach is described that allows an optical disc drive to accurately verify the power level of irradiation beam power levels associated a write strategy used in high speed, high density optical disc media formats using a front monitor diode with a relatively slow rise time and/or relative slow fall time compared to the clock cycle speed of the write strategy signal. A portion of encoded data to be written to an optical disc media may be overwritten to include a predetermined data pattern. During write strategy processing of the data, the predetermined data pattern is replaced with a constant write strategy power level. The constant write strategy output placed within the write strategy signal may control the optical disc drive laser to emit a constant irradiation beam for a duration sufficiently long to allow the front monitor diode to obtain an accurate measure of the irradiation beam power level.

摘要翻译： 描述了一种方法，其允许光盘驱动器使用具有相对较慢的上升时间的前监视二极管来准确地验证与在高速，高密度光盘介质格式中使用的写策略相关联的照射光束功率电平的功率电平和/或 相对于写入策略信号的时钟周期速度相对较慢的下降时间。 要写入光盘介质的编码数据的一部分可以被重写以包括预定的数据模式。 在数据的写入策略处理期间，以恒定写入策略功率电平替换预定数据模式。 放置在写入策略信号内的恒定写入策略输出可以控制光盘驱动激光器发射恒定的照射束持续足够长的持续时间，以允许前监视二极管获得照射光束功率电平的精确测量。

公开(公告)号：US08526131B2

公开(公告)日：2013-09-03

申请号：US12955789

申请日：2010-11-29

申请人： Viswanath Annampedu ,  Jeffrey P. Grundvig ,  Keith R. Bloss ,  Vishal Narielwala

发明人： Viswanath Annampedu ,  Jeffrey P. Grundvig ,  Keith R. Bloss ,  Vishal Narielwala

IPC分类号： G11B5/09

CPC分类号： G11B5/59688 ,  G11B5/09 ,  G11B5/59655 ,  G11B20/10009 ,  G11B20/10435

摘要： Various embodiments of the present invention provide systems and methods for determining head polarity. As an example, a head polarity detection circuit includes: a first computation circuit, a second computation circuit, and an inversion determination circuit. The first computation circuit is operable to sum an absolute value of each sample of a first subset of a series of data samples corresponding to a first phase of an analog input to yield a first sum, and the second computation circuit is operable to sum an absolute value of each sample of a second subset of the series of data samples corresponding to a second phase of the analog input to yield a second sum. The first phase is more than ninety degrees offset from the second phase.

摘要翻译： 本发明的各种实施例提供了用于确定磁头极性的系统和方法。 作为例子，头极性检测电路包括：第一计算电路，第二计算电路和反转确定电路。 第一计算电路可操作地对应于与模拟输入的第一相位相对应的一系列数据样本的第一子集的每个样本的绝对值，以产生第一和，并且第二计算电路可操作以将绝对值 所述一系列数据样本的第二子集的每个采样值对应于模拟输入的第二相，以产生第二和。 第一阶段与第二阶段偏离九十度。

公开(公告)号：US08508879B1

公开(公告)日：2013-08-13

申请号：US12949693

申请日：2010-11-18

申请人： Qiyue Zou ,  Supaket Katchmart ,  Gregory Burd

发明人： Qiyue Zou ,  Supaket Katchmart ,  Gregory Burd

IPC分类号： G11B5/09

CPC分类号： G11B20/1024 ,  G11B5/59616 ,  G11B5/746 ,  G11B20/10435 ,  G11B2220/252

摘要： The present disclosure includes systems and techniques relating to control of magnetic recording devices, such as disk drives. A described technique includes producing signals that include a write clock signal and a servo clock signal, processing a waveform produced by a read head operated with respect to a recording medium, which includes magnetic bit cells arranged on tracks, and the servo clock signal. The technique includes producing, based on the waveform, a servo detect pulse that indicates a detection of servo data, measuring a timing difference that is based on the servo detect pulse and a write pulse of the write clock signal, and controlling an adjustment of a phase of the write clock signal based on the timing difference to align the write clock signal with at least a portion of the bit cells.

摘要翻译： 本公开包括与磁记录装置（例如磁盘驱动器）的控制有关的系统和技术。 所描述的技术包括产生包括写时钟信号和伺服时钟信号的信号，处理由相对于记录介质操作的读取头产生的波形，其包括布置在轨道上的磁位单元和伺服时钟信号。 该技术包括基于波形产生指示伺服数据的检测的伺服检测脉冲，测量基于伺服检测脉冲的定时差和写入时钟信号的写入脉冲，以及控制对 基于定时差来写入时钟信号的相位，以将写入时钟信号与位单元的至少一部分对准。

公开(公告)号：US20120236429A1

公开(公告)日：2012-09-20

申请号：US13050765

申请日：2011-03-17

申请人： Shaohua Yang ,  Changyou Xu ,  Wu Chang ,  Ming Jin

发明人： Shaohua Yang ,  Changyou Xu ,  Wu Chang ,  Ming Jin

IPC分类号： G11B5/09 ,  G11B5/02

CPC分类号： G11B20/1217 ,  G11B20/10435 ,  G11B20/10462 ,  G11B20/1403 ,  G11B2020/1284 ,  G11B2020/1476 ,  G11B2220/2516

摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a read circuit and a combining circuit. The read circuit is operable to provide a first instance of a user data set, a second instance of the user data set, and a third instance of the user data set. The combining circuit is operable to: combine at least a first segment of the first instance of the user data set with a first segment of the second instance of the user data set to yield a first combined data segment; provide a second combined data set that includes a combination of one or more second segments from the second instance of the user data set and the third instance of the user data set; and provide an aggregate data set including at least the first combined data set and the second combined data set. The second combined data set does not incorporate a second segment of the first instance of the user data set.

摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 作为示例，公开了包括读取电路和组合电路的数据处理电路。 读取电路可操作以提供用户数据集的第一实例，用户数据集的第二实例以及用户数据集的第三实例。 组合电路可操作为：将用户数据集的第一实例的至少第一段与用户数据集的第二实例的第一段组合以产生第一组合数据段; 提供第二组合数据集，其包括来自用户数据集的第二实例和用户数据集的第三实例的一个或多个第二段的组合; 并提供包括至少第一组合数据集和第二组合数据集的聚合数据集。 第二组合数据集不包括用户数据集的第一实例的第二段。

公开(公告)号：US20120134042A1

公开(公告)日：2012-05-31

申请号：US12955789

申请日：2010-11-29

申请人： Viswanath Annampedu ,  Jeffrey P. Grundvig ,  Keith R. Bloss ,  Vishal Narielwala

发明人： Viswanath Annampedu ,  Jeffrey P. Grundvig ,  Keith R. Bloss ,  Vishal Narielwala

IPC分类号： G11B27/36

CPC分类号： G11B5/59688 ,  G11B5/09 ,  G11B5/59655 ,  G11B20/10009 ,  G11B20/10435

摘要： Various embodiments of the present invention provide systems and methods for determining head polarity. As an example, a head polarity detection circuit includes: a first computation circuit, a second computation circuit, and an inversion determination circuit. The first computation circuit is operable to sum an absolute value of each sample of a first subset of a series of data samples corresponding to a first phase of an analog input to yield a first sum, and the second computation circuit is operable to sum an absolute value of each sample of a second subset of the series of data samples corresponding to a second phase of the analog input to yield a second sum. The first phase is more than ninety degrees offset from the second phase.

摘要翻译： 本发明的各种实施例提供了用于确定磁头极性的系统和方法。 作为例子，头极性检测电路包括：第一计算电路，第二计算电路和反转确定电路。 第一计算电路可操作地对应于与模拟输入的第一相位相对应的一系列数据样本的第一子集的每个样本的绝对值，以产生第一和，并且第二计算电路可操作以将绝对值 所述一系列数据样本的第二子集的每个采样值对应于模拟输入的第二相，以产生第二和。 第一阶段与第二阶段偏离九十度。

公开(公告)号：US08107180B2

公开(公告)日：2012-01-31

申请号：US12505085

申请日：2009-07-17

申请人： Shuji Nishida ,  Yasutaka Nishida ,  Masafumi Mochizuki ,  Hideaki Maeda

发明人： Shuji Nishida ,  Yasutaka Nishida ,  Masafumi Mochizuki ,  Hideaki Maeda

IPC分类号： G11B5/09 ,  G11B27/36

CPC分类号： G11B5/09 ,  B82Y10/00 ,  G11B5/59616 ,  G11B5/743 ,  G11B20/10009 ,  G11B20/10435 ,  G11B20/1879 ,  G11B2220/2516 ,  G11B2220/252

摘要： A hard-disk drive. The hard-disk drive includes a magnetic-recording disk including tracks on which a plurality of patterned bit-cells that are isolated magnetically are aligned at predetermined alignment pitches. The hard-disk drive includes a magnetic-recording head which is configured to follow tracks, and to write and to read data. The hard-disk drive includes a signal-processing unit which is configured to generate a recording signal based on a write-clock signal with cycles corresponding to alignment pitches of patterned bit-cells, and to output a recording signal. The hard-disk drive includes a phase-detecting unit which is configured to detect a phase of the write-clock signal when the magnetic-recording head reaches an end point of a predetermined range. The hard disk drive includes a determination-processing unit which is configured to determine success of data writing based on a difference between an expected value and a detected value of the phase of the write-clock signal.

摘要翻译： 硬盘驱动器。 硬盘驱动器包括磁记录盘，磁盘包括轨道，磁道上分离出多个图案化的位单元，以预定的对准间距排列。 硬盘驱动器包括磁记录头，其被配置为跟随轨道，并且写入和读取数据。 硬盘驱动器包括信号处理单元，其被配置为基于具有对应于图案化位单元的对准间距的周期的写时钟信号产生记录信号，并输出记录信号。 硬盘驱动器包括相位检测单元，其被配置为当磁记录头达到预定范围的终点时检测写时钟信号的相位。 硬盘驱动器包括确定处理单元，其被配置为基于期望值和写入时钟信号的相位的检测值之间的差来确定数据写入的成功。