公开(公告)号：US5856977A

公开(公告)日：1999-01-05

申请号：US856557

申请日：1997-05-15

申请人： Muh-rong Yang ,  Gin-Kou Ma

发明人： Muh-rong Yang ,  Gin-Kou Ma

IPC分类号： H04L12/56 ,  H04L12/28

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/153 ,  H04L49/1561 ,  H04L2012/5647 ,  H04L2012/5681

摘要： An inventive switch for transporting information cells without cell contention is described. The switch includes at least one parallel distribution network. Each distribution network includes an N.times.N first routing network for receiving cells at a plurality of input ports, where N equals the number the input ports. Illustratively, the routing network is self-routing and non-blocking, such as a Banyan Network. Connected to the N.times.N network are .rho..sup.k groups of shared buffers for storing the cells routed through the network for a period of time not greater than one cell cycle, where k is incremented from 1 to �log.sub.2 N/log.sub.2 .rho.!.sup.-1 and .rho. equals a predetermined speed-up factor. In one aspect of this embodiment, the number of shared buffers is simply equal to N/.rho.. To prevent cell contention and cell loss, all of the contentious cells (cells destined for the same output during the same cycle) are stored in the same shared buffer. Connected to the shared buffers are .rho..sup.k groups of (N/.rho..sup.k).times.(N/.rho..sup.k) routing networks each having a plurality of output ports for outputting the cells, stored in the shared buffers, based on the destination addresses of each cell. Due in part to the utilization of .rho..sup.k groups of shared buffers, a large reduction in both hardware costs and chip real estate is realized. Specifically, a decrease in the number of switching stages is achieved.

摘要翻译： 描述了用于在没有信元争用的情况下传送信息单元的本发明的开关。 交换机包括至少一个并行分发网络。 每个分配网络包括用于在多个输入端口处接收小区的NxN第一路由网络，其中N等于输入端口的数量。 说明性地，路由网络是自路由和非阻塞的，例如Banyan网络。 连接到NxN网络是共享缓冲器组，用于存储经由网络路由的小区不超过一个小区周期，其中k从1增加到[log2N / log2rho] -1，rho等于 预定的加速因子。 在该实施例的一个方面，共享缓冲器的数量简单地等于N / rho。 为了防止信元争用和信元丢失，所有有争议的信元（在相同周期期间注定为相同输出的信元）被存储在相同的共享缓冲器中。 连接到共享缓冲器的是（N / rho k）x（N / rho k）路由网络的rho k组，每个路由网络具有多个输出端口，用于基于每个的目的地地址存储在共享缓冲器中的单元 细胞。 部分由于使用rhok组的共享缓冲区，实现了硬件成本和芯片空间的大幅度降低。 具体地说，实现了切换级数的减少。

公开(公告)号：US5648957A

公开(公告)日：1997-07-15

申请号：US388973

申请日：1995-02-15

申请人： Byoung ki Lee ,  Jung-kyu Lee

发明人： Byoung ki Lee ,  Jung-kyu Lee

IPC分类号： H04Q3/00 ,  H04L12/931 ,  H04L12/933 ,  H04L12/937 ,  H04Q3/52 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/1561 ,  H04L49/255 ,  H04L2012/5681

摘要： A distributor with controlled switching elements (CSE) which simplifies hardware construction by distributing the function of a running adder into a reverse banyan network. The distributor comprises a CSE-based network using switching stages, each switching stage having control switching elements. A control signal input stage switches two packet input signal switching channels, each stage receiving each control signal from an output stage having switching elements. An active packet counter counts and generates an output signal which represents the number of active packets inputted to the CSE network. A tail-of-queue register is used for storing output vectors.

摘要翻译： 具有受控开关元件（CSE）的分配器，其通过将运行中的加法器的功能分配到反向榕树网络来简化硬件构造。 分配器包括使用开关级的基于CSE的网络，每个开关级具有控制开关元件。 控制信号输入级切换两个分组输入信号切换通道，每个级从具有开关元件的输出级接收每个控制信号。 活动分组计数器计数并产生表示输入到CSE网络的活动分组的数量的输出信号。 队列尾寄存器用于存储输出向量。

公开(公告)号：US5539559A

公开(公告)日：1996-07-23

申请号：US934098

申请日：1992-08-21

申请人： Arturo Cisneros ,  Tirunell V. Lakshman

发明人： Arturo Cisneros ,  Tirunell V. Lakshman

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04J14/02

CPC分类号： H04L12/5601 ,  H04L49/1561 ,  H04L49/1576 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/5681

摘要： Apparatus and methods are provided for photonic contention resolution in a switch including a plurality of input modules and a plurality of output modules, wherein at least two of the plurality of input modules have cells to be transmitted to a destination output module. The photonic contention resolution device includes a plurality of coherent light sources for emitting a beam of coherent light and a plurality of tunable receivers. Each of the coherent light sources and tunable receivers are tunable by an associated input module to a plurality of distinct wavelengths. Each tunable laser preferably illuminates at least one of the plurality of tunable receivers at the particular wavelength associated with the destination output module such that one of the at least two input modules transmits its cell to the destination output module if none of the plurality of coherent light sources is illuminating its associated tunable receiver at the particular wavelength.

摘要翻译： 在包括多个输入模块和多个输出模块的开关中提供用于光子争用分辨率的装置和方法，其中多个输入模块中的至少两个具有要发送到目的地输出模块的单元。 光子争用解决装置包括用于发射相干光束的多个相干光源和多个可调接收器。 每个相干光源和可调谐接收器可由相关的输入模块调谐到多个不同的波长。 每个可调谐激光器优选地以与目的地输出模块相关联的特定波长照亮多个可调谐接收器中的至少一个，使得如果不存在多个相干光，则至少两个输入模块中的一个将其单元发送到目的地输出模块 光源在特定波长下照亮其相关联的可调谐接收器。

公开(公告)号：US5361255A

公开(公告)日：1994-11-01

申请号：US693553

申请日：1991-04-29

申请人： Felix V. Diaz ,  Jack H. Stanley

发明人： Felix V. Diaz ,  Jack H. Stanley

IPC分类号： H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04L49/1561 ,  H04L49/1576 ,  H04L49/309 ,  H04Q11/0478 ,  H04L2012/5605 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5681

摘要： A method and apparatus for a high speed asynchronous transfer mode switch is provided which includes an input buffer circuit coupled to communication lines for receiving and temporarily storing packets from the communication lines, a switch comprising one or more planes and output circuitry for coupling the switch outputs to respective communication lines. The switch is comprised of a plurality of switching elements, each of which include a sorter for ranking packets responsive to addresses associated with the packets, compare circuitry for receiving the ranked packets from the sorter and passing up to a predetermined number of packets having the same address, and routing circuitry for routing the packets passed by the compare circuitry responsive to the associated addresses. After a packet is successfully transferred through the switch, an acknowledge signal is returned to the sending input buffer circuit.

摘要翻译： 提供了一种用于高速异步传输模式切换的方法和装置，其包括耦合到通信线路的输入缓冲电路，用于接收和临时存储来自通信线路的分组，包括一个或多个平面的开关和用于耦合开关输出的输出电路 到相应的通信线路。 交换机包括多个交换元件，每个开关元件包括分类器，用于响应于与分组相关联的地址对分组进行排序，比较电路，用于从分类器接收排序分组，并传递到具有相同分组的预定数量的分组 地址和路由电路，用于响应于相关联的地址路由由比较电路传递的分组。 通过交换机成功传输数据包后，将确认信号返回给发送输入缓冲电路。

公开(公告)号：US5258752A

公开(公告)日：1993-11-02

申请号：US686837

申请日：1991-04-17

申请人： Naoki Fukaya ,  Yutaka Kakuno

发明人： Naoki Fukaya ,  Yutaka Kakuno

IPC分类号： H04L12/56 ,  H04Q1/00

CPC分类号： H04L12/5601 ,  H04L49/106 ,  H04L49/1561 ,  H04L49/255 ,  H04L49/405 ,  H04L2012/5627 ,  H04L2012/5651 ,  H04L2012/5679 ,  Y10T307/74

摘要： A broad band digital exchange is provided which includes a Banyan network or Batcher Banyan network which is used in an ATM machine for selectively connecting digital information. In such networks, cells which retain information may conflict so that the cell is discarded. Thus, all input information is not always transmitted. In order to lower the cell discard rate, various techniques have been proposed. In the present invention, an identification bit is provided in a header of the cell. When cells conflict, the identification bit of the losing cell is set so that the losing cell does not impede the transmission of information contained in the other cell. In another aspect, when cells conflict, a conflict detection signal is sent back to a buffer controller which controls the send-out of the information cells. In another aspect, the conflict detection signal is sent back to the buffer controller through a path through which the losing cell has been supplied. When the buffer controller receives such conflict detection signal, it resends the information of the losing cell stored in the buffer memory. As a result, the discard rate of the cells is lowered and the required hardware of the network is reduced.

摘要翻译： 提供了一种宽带数字交换机，其包括在ATM机中用于选择性地连接数字信息的Banyan网络或Batcher Banyan网络。 在这样的网络中，保留信息的小区可能会相冲突，以致该小区被丢弃。 因此，所有输入信息并不总是被发送。 为了降低细胞丢弃率，提出了各种技术。 在本发明中，在单元的标题中提供识别位。 当小区冲突时，设置丢失小区的标识位，使得丢失小区不妨碍包含在另一个小区中的信息的传输。 在另一方面，当小区冲突时，将冲突检测信号发送回控制信息单元发送的缓冲器控制器。 在另一方面，冲突检测信号通过已经提供了丢失单元的路径被发送回缓冲器控制器。 当缓冲器控制器接收到这种冲突检测信号时，它重新发送存储在缓冲存储器中的丢失单元的信息。 结果，小区的丢弃速率降低，网络所需的硬件减少。

公开(公告)号：US5157654A

公开(公告)日：1992-10-20

申请号：US629576

申请日：1990-12-18

申请人： Arturo Cisneros

发明人： Arturo Cisneros

IPC分类号： H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04L49/1561 ,  H04L49/1576 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/5681

摘要： Apparatus, and accompanying methods for use therein, for a large (e.g. approximately 1 Terabit/second), fault tolerant packet switch (200), particularly suited for asynchronous mode transfer (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel, planes of self-routing cross-points (550), staggered time phased contention resolution and shared memory based input and output modules (260 and 270, respectively). The contention resolution involves storing for each input packet in two registers the address of the incoming packet and an indication of whether that packet had priorly lost a contention resolution. In that way a fairness factor is added to the contention resolution.

摘要翻译： 对于大型（例如大约1兆比特/秒）容错分组交换机（200），特别适用于异步模式传输（ATM）通信的大型（例如大约1兆比特/秒）的装置及其附带的方法，其特别适用于与小区地址一起使用的小区地址 平行的自路由交叉点（550），交错时间相位争用解决方案和基于共享内存的输入和输出模块（分别为260和270）。 争用解决方案涉及将两个寄存器中的每个输入分组存储到输入分组的地址以及该分组先前是否丢失争用解决的指示。 以这种方式，公正因素被添加到争用解决方案中。

公开(公告)号：US4891803A

公开(公告)日：1990-01-02

申请号：US267606

申请日：1988-11-07

申请人： Alan Huang ,  Scott C. Knauer ,  Jay H. O'Neill ,  Charles W. Rutledge ,  Sheng L. Lin ,  Maurice N. Ransom ,  Ronald A. Spanke

发明人： Alan Huang ,  Scott C. Knauer ,  Jay H. O'Neill ,  Charles W. Rutledge ,  Sheng L. Lin ,  Maurice N. Ransom ,  Ronald A. Spanke

IPC分类号： H04L12/56

CPC分类号： H04L12/5601 ,  H04L47/10 ,  H04L49/106 ,  H04L49/1553 ,  H04L49/1561 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5681

摘要： A packet switching network that accommodates the appearance of multiple occurrences of packets addressed to the same destination are accommodated. The network includes a recirculating delay block within the switch, and an expander that includes a modest number of multiple appearances of the same address, followed by memories that accept the packets delivered at those multiple appearances, store the packets, and output the stored packets to the user, one at a time, in accordance with a set priority scheme.

公开(公告)号：US4829227A

公开(公告)日：1989-05-09

申请号：US139464

申请日：1987-12-30

申请人： Jonathan S. Turner

发明人： Jonathan S. Turner

IPC分类号： H04Q11/04 ,  H04L12/18 ,  H04L12/54 ,  H04L12/56 ,  H04L12/58

CPC分类号： H04L49/505 ,  H04L12/1854 ,  H04L49/106 ,  H04L49/1561 ,  H04L49/201 ,  H04L49/203 ,  H04L2012/5652 ,  H04L49/1507 ,  H04L49/25 ,  H04L49/253 ,  H04L49/254 ,  H04L49/30 ,  H04L49/357 ,  H04L49/557

摘要： A high bit rate data link is disclosed. The high bit rate data link comprises a group of individual low bit rate data links. A memory stores the addresses of all the low bit rate data links in the group. The memory is indexed by packets including an identification number for the group. The addresses of the low bit rate links are successively written into packets containing the group identification number so that these packets are evenly distributed to the low bit rate links comprising the group.

摘要翻译： 公开了一种高比特率数据链路。 高比特率数据链路包括一组单独的低比特率数据链路。 存储器存储组中所有低比特率数据链路的地址。 存储器由包括组的标识号的分组索引。 低比特率链路的地址被连续地写入包含组标识号的分组，使得这些分组被均匀地分配到包括组的低比特率链路。

公开(公告)号：US20240314226A1

公开(公告)日：2024-09-19

申请号：US18183591

申请日：2023-03-14

申请人： Nokia Solutions and Networks Oy

发明人： Pranjal Kumar Dutta

IPC分类号： H04L69/22 ,  H04L45/00 ,  H04L49/15 ,  H04L49/25

CPC分类号： H04L69/22 ,  H04L45/566 ,  H04L49/1561 ,  H04L49/25

摘要： Various example embodiments for supporting communication of inter-card control messages in a router chassis are presented herein. The communication of an inter-card control message in a router chassis may be performed using a data packet sent over a switch fabric of the router chassis. The data packet may include a payload and a data packet header, where the payload includes the inter-card control message and the data packet header includes an indication that the data packet includes the inter-card control message. The inter-card control message may be sent over the switch fabric indirectly using a data packet protocol header encapsulating the payload and a switch fabric header encapsulating the data packet protocol header. The inter-card control message may be sent over the switch fabric directly using a switch fabric header encapsulating the payload.

公开(公告)号：US20160255019A1

公开(公告)日：2016-09-01

申请号：US15151071

申请日：2016-05-10

申请人： Juniper Networks, Inc.

发明人： Gunes AYBAY

IPC分类号： H04L12/935 ,  H04L12/743 ,  H04L29/06 ,  H04L12/947

CPC分类号： H04L49/3009 ,  H04L12/5601 ,  H04L45/74 ,  H04L45/7453 ,  H04L49/101 ,  H04L49/1515 ,  H04L49/1561 ,  H04L49/1569 ,  H04L49/1576 ,  H04L49/25 ,  H04L49/256 ,  H04L69/22

摘要： A method of sending data to a switch fabric includes assigning a destination port of an output module to a data packet based on at least one field in a first header of the data packet. A module associated with a first stage of the switch fabric is selected based on at least one field in the first header. A second header is appended to the data packet. The second header includes an identifier associated with the destination port of the output module. The data packet is sent to the module associated with the first stage. The module associated with the first stage is configured to send the data packet to a module associated with a second stage of the switch fabric based on the second header.