公开(公告)号：US11048844B1

公开(公告)日：2021-06-29

申请号：US16913657

申请日：2020-06-26

申请人： Graphcore Limited

发明人： Paul Miseldine ,  Michael Davie

IPC分类号： G06F30/33 ,  G06F30/3323 ,  G06F119/16

摘要： A method and system for improved design verification for a data processing device when performing a logic simulation. The system identifies certain corresponding coverpoints at different points in results of a logic simulation for a design. Using coverage results obtained for the design, a merging of the results is performed for the certain corresponding coverpoints in the design. In the merged results, a coverpoint is considered as covered if at least one corresponding coverpoint is covered during the logic simulation.

公开(公告)号：US11030369B2

公开(公告)日：2021-06-08

申请号：US16559874

申请日：2019-09-04

申请人： Microsoft Technology Licensing, LLC

发明人： Janet L. Schneider ,  Kenneth Reneris ,  Mark G. Kupferschmidt ,  Brian L. Koehler ,  Adam J. Muff ,  Alexander L. Braun ,  Alison Ii

IPC分类号： G06F30/30 ,  G06F30/3323 ,  G06F30/3312 ,  G06F30/327 ,  G06F30/337 ,  G06F1/12 ,  H03K3/38 ,  G06F30/398 ,  G06F119/12 ,  G06F30/392 ,  G06F30/396 ,  G06F119/16

摘要： Superconducting circuit with virtual timing elements and related methods are described. A method includes specifying a superconducting circuit portion including a timing path comprising: (1) at least one logic gate to be implemented using Josephson junctions, (2) a first virtual timing element for defining a synchronization point along the timing path, and (3) a second virtual timing element for adding latency to the timing path. The method further includes synthesizing the superconducting circuit portion, where the synthesizing comprises treating the first virtual timing element as a first flip-flop and the second virtual timing element as a second flip-flop, where the first flip-flop is treated as being fixed in relation to the at least one logic gate along the timing path, but the second flip-flop is treated as being movable in relation to the at least one logic gate along the timing path.

公开(公告)号：US10984161B1

公开(公告)日：2021-04-20

申请号：US16689410

申请日：2019-11-20

申请人： Cadence Design Systems, Inc.

发明人： Rajdeep Mukherjee ,  Ravi Prakash ,  Benjamin Meng-Ching Chen ,  Habeeb Farah ,  Ziyad Hanna

IPC分类号： G06F30/3323 ,  G06F111/02 ,  G06F119/16

摘要： The present disclosure relates to a computer-implemented method for use in a formal verification of an electronic design. Embodiments may include receiving a reference model including a software specification, an implementation model at a register transfer level, and a property that analyzes equivalence between the reference model and the implementation model. The method may further include generating one or more case split hints based upon the reference model, that may be used to decompose the design state space into smaller partitions and performing an abstraction operation on a portion of design logic associated with one or more partitions in order to eliminate design elements that are irrelevant to a particular property. Embodiments may also include performing model checking on the abstract models to determine their accuracy.

公开(公告)号：US10970444B1

公开(公告)日：2021-04-06

申请号：US16989347

申请日：2020-08-10

申请人： International Business Machines Corporation

发明人： Bradley Donald Bingham ,  Viresh Paruthi ,  Abrar Polani

IPC分类号： G06F17/50 ,  G01R31/00 ,  G06F30/33 ,  G01R31/317 ,  G06F30/3323 ,  G06F30/337 ,  G06F119/16

摘要： A method and/or system is disclosed for pre-silicon verification of a first integrated circuit design modified to a second integrated circuit design to avoid a hit of property P where property P has a known counterexample. The method/system includes applying a first implication check in an equivalence testbench on the first integrated circuit and on the second integrated circuit to determine whether the second integrated circuit hits property P in the same way as the first integrated circuit hits property P. Additionally or alternatively applying a second implication check to determine whether the second integrated circuit hits property P at a different timestep than the first integrated circuit hits property P. Additionally or alternatively applying a third implication check to determine whether the second integrated circuit hits property P further along a path than the first integrated circuit hits property P.

公开(公告)号：US10789404B1

公开(公告)日：2020-09-29

申请号：US16434129

申请日：2019-06-06

申请人： Cadence Design Systems, Inc.

发明人： Rajdeep Mukherjee ,  Benjamin Meng-Ching Chen ,  Habeeb Farah ,  Ziyad Hanna

IPC分类号： G06F17/50 ,  G06F30/33 ,  G06F30/3323 ,  G06F30/327 ,  G06F30/31 ,  G06F30/323 ,  G06F30/30 ,  G06F111/02 ,  G06F119/16

摘要： The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a specification model associated with an electronic design and generating, using a parser, an intermediate representation based upon, at least in part, the specification model. Embodiments may also include applying a machine generated semantic preserving program transformation to the intermediate representation to create a semantically transformed specification model and synthesizing the semantically transformed specification model to generate a formal verification model.