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    Processing Unit
    1.
    发明公开
    Processing Unit 审中-公开

    公开(公告)号：US20240296010A1

    公开(公告)日：2024-09-05

    申请号：US18591349

    申请日：2024-02-29

    Applicant: Graphcore Limited

    Inventor： Thomas BROWN

    IPC: G06F7/499 ,  G06F7/523 ,  G06F7/556

    CPC classification number: G06F7/49915 ,  G06F7/523 ,  G06F7/556

    Abstract: A processing unit is provided with circuitry enabling execution quick evaluation of an exponential function. A multiplier circuit is used to multiply the input operand by log2(e), such that a result for the exponential function may be determined by evaluating 2i+f, where i is an integer part of a fixed-point number and f is a fractional part of the fixed-point number. A lookup table is used for providing an estimate for 2f based on the l MSBs of f. The lookup entries are provided according to a function such that the estimates for 2f are provided without bias towards either zero or infinity in the result. In other words, the maximum multiplicative error for each entry of the lookup table is the same in both negative and positive directions. In this way, statistical errors in the evaluation of a large number of exponential functions may be avoided.

    Block cipher encryption pipeline
    3.
    发明授权
    Block cipher encryption pipeline 有权

    公开(公告)号：US12047486B2

    公开(公告)日：2024-07-23

    申请号：US17359066

    申请日：2021-06-25

    Applicant: Graphcore Limited

    Inventor： Graham Cunningham

    IPC: H04L9/06

    CPC classification number: H04L9/0618 ,  H04L9/0643

    Abstract: The device implements a processing pipeline having distinct circuitry for performing encryption/decryption operations and authentication operations and having state stores associated with the respective operations. The state stores store state associated with a given encryption frame, enabling the respective operations to be performed when blocks of data reach that stage in the pipeline. Due to the complexity of operations in a block cipher encryption scheme, the pipeline is deep, which provide the possibility for processing multiple data packets at any one time. The provision of the state stores at the stages in the pipeline at which they are required prevents stalling when a new data packet is received.

    System and Method for Synchronising Access to Shared Memory
    4.
    发明公开
    System and Method for Synchronising Access to Shared Memory 审中-公开

    公开(公告)号：US20240095103A1

    公开(公告)日：2024-03-21

    申请号：US18458327

    申请日：2023-08-30

    Applicant: Graphcore Limited

    Inventor： Lars Paul HUSE ,  Uberto GIROLA ,  Bjorn Dag JOHNSEN

    IPC: G06F9/54 ,  G06F9/38

    CPC classification number: G06F9/544 ,  G06F9/3836

    Abstract: A read and notify request is issued by a first processing unit to a lock manager on a different chip. A lock manager determines whether a condition specified by the request in relation to a variable for controlling access to a memory buffer is met. If the two are not equal, a notification request is registered until the variable changes. The second processing unit accesses the memory buffer and, when it has finished, updates the variable. If the variable then satisfies the condition specified by the read and notify request, the first processing unit is then notified by the lock manager and accesses the memory buffer. In this way, the first processing unit does not need to continually poll to determine when the variable has changed, but is notified when it is its turn to access the memory buffer.

    Clearing register data using a write enable signal
    8.
    发明授权
    Clearing register data using a write enable signal 有权

    公开(公告)号：US11847455B2

    公开(公告)日：2023-12-19

    申请号：US17345186

    申请日：2021-06-11

    Applicant: Graphcore Limited

    Inventor： Jonathan Louis Ferguson

    IPC: G06F9/30 ,  G06F15/78

    CPC classification number: G06F9/30141 ,  G06F9/3016 ,  G06F15/7807

    Abstract: A processing unit having a register file includes: a plurality of registers each having a write enable input configured to receive a write enable signal and a write data input connected to a write data path of the processing unit and configured to write data values from the write data path for storage in a register when the write enable signal is asserted; write circuitry configured in a normal mode of operation to assert the write enable signal of a respective one of the registers to cause operational data values to be written to that register from the write data path; and data cleansing circuitry configured to control a data cleansing mode in which write enable signals of all registers in the register file are simultaneously asserted to cause cleansing data values to be simultaneously written to all registers in the register file from the write data path.

    External Exchange Connectivity
    10.
    发明公开
    External Exchange Connectivity 审中-公开

    公开(公告)号：US20230281144A1

    公开(公告)日：2023-09-07

    申请号：US17658944

    申请日：2022-04-12

    Applicant: Graphcore Limited

    Inventor： Daniel WILKINSON ,  Stephen FELIX ,  Simon KNOWLES ,  Graham CUNNINGHAM ,  David LACEY

    IPC: G06F13/40 ,  G06F9/30 ,  G06F9/52

    CPC classification number: G06F13/4022 ,  G06F9/30079 ,  G06F9/522 ,  G06F13/4027

    Abstract: A processing device has a plurality of interfaces and a plurality of processors. During different phases of execution of a computer program, different processors are associated with different interfaces, such that the connectivity between processors and interfaces for the sending of egress data and the receiving of ingress data may change during execution of that computer program. The change in this connectivity is directed by the compiled code running on the processors. The compiled code selects which buses associated with which interfaces, given processors are to connect to for receipt of ingress data. Furthermore, the compiled code causes control messages to be sent to circuitry associated with the interfaces, so as to control which buses associated with which processors, given interfaces are to connect to.

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