公开(公告)号：US20210406197A1

公开(公告)日：2021-12-30

申请号：US16910813

申请日：2020-06-24

申请人： IDEX Biometrics ASA

发明人： Matthew Henry

IPC分类号： G06F12/1045 ,  G06F12/109 ,  G06F12/02 ,  G06F12/0884 ,  G06F12/06 ,  G06F9/30

摘要： A cache includes a p-by-q array of memory units; a row addressing unit; and a column addressing unit. Each memory unit has an m-by-n array of memory cells. The column addressing unit has, for each memory unit, m n-to-one multiplexers, one associated with each of the m rows of the memory unit, wherein each n-to-one multiplexer has an input coupled to each of the n memory cells associated with the row associated with that multiplexer. The row addressing unit has, for each memory unit, n m-to-one multiplexers, one associated with each of the n columns of the memory unit, wherein each m-to-one multiplexer has an input coupled to each of the m memory cells associated with the column associated with that multiplexer. The row addressing unit and column addressing unit support reading and/or writing of the array of memory units, e.g. using virtual or physical addresses.

公开(公告)号：US20210406050A1

公开(公告)日：2021-12-30

申请号：US16490474

申请日：2017-03-31

申请人： Intel Corporation

发明人： Peng HUANG ,  Liang LI ,  Xiaofeng HUANG

IPC分类号： G06F9/455 ,  G06F9/48 ,  G06F12/109

摘要： Examples may include techniques to decrease a live migration time for a virtual machine (VM). Examples include selecting data to copy or not copy during a live migration of the VM from a source host server to a destination host server.

公开(公告)号：US11176040B2

公开(公告)日：2021-11-16

申请号：US16835024

申请日：2020-03-30

申请人： Netlist, Inc.

发明人： Hyun Lee ,  Junkil Ryu

IPC分类号： G06F12/10 ,  G06F12/0813 ,  G06F9/455 ,  G06F13/00 ,  H04L29/08 ,  G06F12/109 ,  G06F12/02 ,  G06F12/1045

摘要： The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes each having at least one UMA memory unit and a server local to the at least one UMA memory unit. A respective UMA memory unit in a respective UMA node comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on the local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes. Thus, a server in the UMA network can access the physical address spaces at other UMA nodes without going through the servers in the other UMA nodes.

公开(公告)号：US11163454B1

公开(公告)日：2021-11-02

申请号：US15799433

申请日：2017-10-31

申请人： EMC IP Holding Company, LLC

发明人： Nickolay Dalmatov ,  Michael P. Wahl ,  Jian Gao

IPC分类号： G06F3/06 ,  G06F12/109

摘要： A method, computer program product, and computing system for compartmentalizing a plurality of RAID extents, within a RAID system, into a plurality of rotation subgroups. An IO overload condition is sensed in at least one drive extent associated with a first rotation subgroup, chosen from the plurality of rotation subgroups. Instructions are provided concerning moving at least a portion of a load experienced by the first rotation subgroup to a second rotation subgroup, chosen from the plurality of rotation subgroups.

公开(公告)号：US11119931B1

公开(公告)日：2021-09-14

申请号：US16575196

申请日：2019-09-18

申请人： Facebook Technologies, LLC

发明人： Christoph Klee ,  Bernhard Poess

IPC分类号： G06F12/00 ,  G06F12/0855 ,  G06F12/0873 ,  G06F9/54 ,  G06F12/14 ,  G06F12/109

摘要： In one embodiment, a method includes receiving a request to create a data pipeline by an operating system executing on a computing device. The operating system allocates a shared virtual memory region for the data pipeline. The shared virtual memory region is mapped to a first virtual address space of a first process and a second virtual address space of a second process. The mapping enables the first process and the second process to share data through the shared virtual memory region. Membership information associated with the data pipeline is updated to include the first process and the second process. An access request for accessing the shared virtual memory region is received from the first process, and the access request is granted or denied based on one or more protection policies.

公开(公告)号：US11074195B2

公开(公告)日：2021-07-27

申请号：US16456006

申请日：2019-06-28

申请人： International Business Machines Corporation

发明人： Elpida Tzortzatos ,  Steven M. Partlow ,  Scott B. Compton ,  Christine Michele Yost ,  Peter Jeremy Relson

IPC分类号： G06F12/10 ,  G06F12/109

摘要： A computer-implemented method for switching between a full space and a subspace across multiple address spaces is described. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space and the subspace is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled and switches, by the processor, the context of the multiple spaces based on determining that the new context is different from the existing context.

公开(公告)号：US11068400B2

公开(公告)日：2021-07-20

申请号：US16256571

申请日：2019-01-24

申请人： VMware, Inc.

发明人： Aasheesh Kolli ,  Irina Calciu ,  Jayneel Gandhi ,  Pratap Subrahmanyam

IPC分类号： G06F12/0831 ,  G06F12/109 ,  G06F9/50 ,  G06F11/07 ,  G06F12/0817

摘要： Disclosed is a technique in which an application can record changes it makes to physical memory. In the technique, the application specifies a virtual memory region which is converted to a plurality of cache lines, each of which is monitored for changes by a device connected to a coherence interconnect coupled to the processor caches. The application sends a start signal to start the logging process and an end signal to stop the process. During the logging process, when a change occurs to one of the cache lines, an undo entry corresponding to the change is created and entered into a transaction log residing in persistent memory. The transaction log containing the undo entries makes the set of changes recorded in the transaction log atomic. If a failure occurs, the recorded changes can be undone as if they never occurred.

公开(公告)号：US11048643B1

公开(公告)日：2021-06-29

申请号：US16808320

申请日：2020-03-03

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/109 ,  G06F12/02

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

公开(公告)号：US11036533B2

公开(公告)日：2021-06-15

申请号：US15959108

申请日：2018-04-20

申请人： Samsung Electronics Co., Ltd.

发明人： Oscar P. Pinto

IPC分类号： G06F9/455 ,  G06F12/02 ,  G06F12/109 ,  G06F9/50 ,  G06F13/00 ,  H04L12/863

摘要： A storage device is disclosed. The storage device may include storage for data and at least one Input/Output (I/O) queue for requests from at least one virtual machine (VM) on a host device. The storage device may support an I/O queue creation command to request the allocation of an I/O queue for a VM. The I/O queue creation command may include an LBA range attribute for a range of Logical Block Addresses (LBAs) to be associated with the I/O queue. The storage device may map the range of LBAs to a range of Physical Block Addresses (PBAs) in the storage.

公开(公告)号：US11023387B1

公开(公告)日：2021-06-01

申请号：US16783100

申请日：2020-02-05

申请人： Radian Memory Systems, Inc.

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/109 ,  G06F12/02

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.