公开(公告)号：US20220238977A1

公开(公告)日：2022-07-28

申请号：US17585212

申请日：2022-01-26

申请人： MPICS INNOVATIONS PTE. LTD

发明人： Kok Keong Richard LUM

IPC分类号： H01P1/36 ,  H03K5/1252

摘要： An isolator, circuit, and isolation method are disclosed. An illustrative capacitive isolator is disclosed to include an input side that receives an electrical input signal, an output side that outputs an electrical output signal, and an isolation barrier that electrically isolates the input side from the output side. The input side is further disclosed to include an array of input capacitors, where each capacitor in the array of input capacitors receives an input pulse based on the electrical input signal, where each capacitor in the array of input capacitors receives the input pulse offset from input pulses received at others of the capacitors in the array of input capacitors thereby extending a pulse duration of the electrical input signal.

公开(公告)号：US20220209756A1

公开(公告)日：2022-06-30

申请号：US17135395

申请日：2020-12-28

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Vibha GOENKA

IPC分类号： H03K5/1252 ,  H03K3/017 ,  H03K3/037 ,  H03K5/24 ,  H03K19/20

摘要： A circuit includes a first delay filter, a first comparator, an inverter, a second delay filter, a second comparator, an OR gate, and a latch. A first delay filter input is coupled to an inverter input. The first comparator has a first comparator input coupled to a first delay filter output and a second comparator input. The second delay filter has an input coupled to an inverter output. The second comparator has a third comparator input coupled to a second delay filter output, and a fourth comparator input coupled to the second comparator input. The OR gate has an input coupled to a first comparator output and another input coupled to a second comparator output. The latch has a clock input coupled to an OR gate output and a latch input coupled to the inverter input. A latch output provides a deglitched signal.

公开(公告)号：US11356083B1

公开(公告)日：2022-06-07

申请号：US17326072

申请日：2021-05-20

申请人： GigaHz Instruments Inc.

发明人： Syama Nediyanchath ,  Paul L. Vella

IPC分类号： H03K5/00 ,  H03K5/1252 ,  H03K5/01

摘要： The present invention is directed to a frequency synthesizer with an improved architecture that eliminates a VCO and a method to build frequency synthesizers for generating high-frequency signals with low phase noise, low spurious, extremely fast switching speed and fine frequency resolution. The synthesizer provides significant improvement in performance, phase noise, switching speed, power, size and cost reduction.

公开(公告)号：US11283434B2

公开(公告)日：2022-03-22

申请号：US17241499

申请日：2021-04-27

申请人： Infineon Technologies LLC

发明人： Eran Geyari ,  Oren Shlomo ,  Yair Sofer ,  Avri Harush

IPC分类号： H03K5/125 ,  H03K5/1252 ,  H03K5/153 ,  H03K5/19 ,  G11C7/20 ,  H03K17/24 ,  G11C7/02 ,  H03K17/22

摘要： A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

公开(公告)号：US20220060182A1

公开(公告)日：2022-02-24

申请号：US17415158

申请日：2019-11-21

申请人： Endress+Hauser SE+Co. KG

发明人： Ghislain Daufeld ,  Arnd Kempa ,  Roland Grozinger ,  Stefan Scherr

IPC分类号： H03K5/1252 ,  H03K19/20 ,  H04B1/04

摘要： Disclosed is a transmitting device comprising two galvanically isolated sub-circuits. The first sub-circuit comprises: a carrier signal source for outputting a carrier signal; a digital signal source for outputting binary signal levels; and a logic component for performing an AND operation on two input signals. The second sub-circuit comprises: a signal input; a signal output; and a first RC element, the signal input, the signal output and the RC element being connected in parallel to one another with respect to a second reference potential. A first isolating capacitor is connected between the first logic output and the signal input for galvanic isolation. A second isolating capacitor is connected between the first reference potential and the second reference potential for galvanic isolation.

公开(公告)号：US11258432B1

公开(公告)日：2022-02-22

申请号：US17125561

申请日：2020-12-17

申请人： Silicon Laboratories Inc.

发明人： Péter Onódy ,  András V. Horváth

IPC分类号： H03K5/125 ,  H03K5/1252 ,  H03H11/06 ,  H03H11/26 ,  H03K3/012 ,  H03K17/687 ,  H03K19/20

摘要： A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

公开(公告)号：US20220014180A1

公开(公告)日：2022-01-13

申请号：US17241447

申请日：2021-04-27

申请人： Infineon Technologies LLC

发明人： Oren Shlomo

IPC分类号： H03K5/1252 ,  H03K5/153 ,  H03K5/24 ,  G01R19/25 ,  G11C7/02 ,  G11C7/10 ,  G11C7/20 ,  G11C7/14

摘要： A voltage-glitch detection and protection circuit and method are provided. Generally, circuit includes a voltage-glitch-detection-block (GDB) and a system-reset-block coupled to the GDB to generate a reset-signal to cause devices in a chip including the circuit to be reset when a voltage-glitch in a supply voltage (VDD) is detected. The GDB includes a voltage-glitch-detector coupled to a latch. The voltage-glitch-detector detects the voltage-glitch and generates a PULSE to the system-reset-block and latch. The latch receives the PULSE and generates a PULSE_LATCHED signal to the system-reset-block to ensure the reset-signal is generated no matter a width of the PULSE. In one embodiment, the latch includes a filter and a sample and hold circuit to power the latch, and ensure the PULSE_LATCHED signal is coupled to the system-reset-block when a voltage to the GDB or to the latch drops below a minimum voltage due to the voltage-glitch.

公开(公告)号：US11183992B1

公开(公告)日：2021-11-23

申请号：US16852729

申请日：2020-04-20

申请人： Xilinx, Inc.

发明人： Roswald Francis ,  Bruno Miguel Vaz

IPC分类号： H03K5/02 ,  H03K5/1252

摘要： A signal buffer is disclosed. The signal buffer may include one or more bias signal generators to bias one or more transistors. The bias signal generators may generate power supply compensated or ground compensated bias signals. The bias signal generators may include a capacitor to provide a high frequency signal path.

公开(公告)号：US11177799B2

公开(公告)日：2021-11-16

申请号：US17029631

申请日：2020-09-23

申请人： STMicroelectronics International N.V.

发明人： Ankur Bal ,  Vikas Chelani

IPC分类号： H03K5/1252 ,  H03K19/003 ,  H03K17/16

摘要： A debounce circuit and a method for masking or filtering a glitch from an input signal are provided. The debounce circuit includes a reset synchronizer circuit and a logic circuit. The reset synchronizer circuit receives the input signal, detects a glitch in the input signal and outputs one or more reset synchronizer output signals having a first reset synchronizer state indicating detection of the glitch. The logic circuit receives the one or more reset synchronizer output signals, determines that the one or more reset synchronizer output signals are in the first reset synchronizer state indicating detection of the glitch and in response to determining that the one or more reset synchronizer output signals are in the first reset synchronizer state, keeps an output signal of the debounce circuit in a present state of the output signal of the debounce circuit.

公开(公告)号：US20210302499A1

公开(公告)日：2021-09-30

申请号：US17267161

申请日：2019-07-16

申请人： Nippon Telegraph and Telephone Corporation

发明人： Takaaki HISASHIMA ,  Hiroki SAKUMA ,  Kaoru ARAI ,  Ryuta SUGIYAMA ,  Shunichi TSUBOI ,  Osamu KUROKAWA ,  Kazuyuki MATSUMURA

IPC分类号： G01R31/317 ,  H03K5/26 ,  H03K5/00 ,  H03K5/1252 ,  G06F1/12

摘要： [Problem] To monitor a frequency difference between an input clock and a synchronous clock synchronized with the input clock.
[Solution] A clock frequency monitoring apparatus that monitors the frequency of an input clock 18a includes a phase comparator 12 that compares a phase of a synchronous clock 18e phase-synchronized with the input clock 18a or a first frequency-divided clock 18f obtained by frequency-dividing the synchronous clock 18e with the phase of the input clock 18a, a filter 13 that low-pass filters an output signal of the phase comparator 12, an oscillator 14 that generates the synchronous clock 18e having a frequency corresponding to a control value from the filter 13, and a determiner 19 that determines that the frequency of the input clock 18a is abnormal when the variation amplitude of the output signal of the filter 13 is equal to or more than a predetermined range.