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    Overvoltage and Surge Protection in a Power Over Ethernet Device
    3.
    发明申请
    Overvoltage and Surge Protection in a Power Over Ethernet Device 有权
    以太网供电中的过电压和浪涌保护

    公开(公告)号：US20170019262A1

    公开(公告)日：2017-01-19

    申请号：US14800616

    申请日：2015-07-15

    Applicant: Silicon Laboratories Inc.

    Inventor： Vince András Horváth ,  Tamás Marozsák ,  Péter Onódy ,  John Gammel

    IPC: H04L12/10

    CPC classification number: H02M1/36 ,  H02H9/041 ,  H02M1/32

    Abstract: In some embodiments, powered devices, circuits, and methods are disclosed that may include biasing a hot swap switch to couple a capacitor of a DC-DC converter to negative supply node when an input voltage exceeds a threshold and biasing a telephony switch to couple a positive supply node to a negative supply node when the input voltage exceeds the threshold. Further, the method may further include deactivating the hot swap switch after a period of time, and continuing to bias the telephony switch.

    Abstract translation: 在一些实施例中，公开了供电设备，电路和方法，其可以包括当输入电压超过阈值时偏置热交换开关以将DC-DC转换器的电容器耦合到负电源节点，并且偏置电话交换机以耦合 当输入电压超过阈值时，正电源节点连接到负电源节点。 此外，该方法还可以包括在一段时间后停用热插拔开关，并且继续偏置电话交换机。

    DAC current source matrix patterns with gradient error cancellation
    4.
    发明授权
    DAC current source matrix patterns with gradient error cancellation 有权
    DAC电流源矩阵模式与梯度误差消除

    公开(公告)号：US09094042B2

    公开(公告)日：2015-07-28

    申请号：US13963788

    申请日：2013-08-09

    Applicant: Silicon Laboratories Inc.

    Inventor： Péter Onódy ,  Abdulkerim L. Coban

    IPC: H03M1/66

    CPC classification number: H03M1/66 ,  H03M1/0648 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

    Abstract: First order gradient errors are canceled with no current source splitting by placing consecutive current sources symmetrically around the center of the array. Consecutive elements that correspond to small input amplitudes (mid-scale codes) make a smaller spatial jump than those correspond to larger signal amplitudes. Both linear and second order gradients are reduced by splitting each current cell into two and placing sub-elements symmetrically with respect to the center of the array to address the linear gradient effect. To address second order gradients, current element placement follows a pattern such that consecutive element pairs are chosen with one of the pair being placed with respect to the zero error contour of the second order gradient so as to have a positive error and the second of the pair being placed so as to have a negative error resulting in reduced second order error accumulation.

    Abstract translation: 通过将连续的电流源对称地围绕阵列的中心来消除第一阶梯度误差，没有电流源分裂。 对应于小输入幅度（中等尺度代码）的连续元件比对应于较大信号幅度的空间跳跃小。 通过将每个当前单元分成两个并将子元素相对于阵列的中心对称放置以解决线性梯度效应，可以减少线性和二阶梯度。 为了解决二阶梯度，当前元素放置遵循模式，使得连续的元素对被选择，其中一对中的一个相对于二阶梯度的零误差轮廓被放置，以便具有正的误差，而第二个 对被放置成具有导致减少的二阶误差累积的负误差。

    Deglitcher circuit with integrated non-overlap function
    5.
    发明授权
    Deglitcher circuit with integrated non-overlap function 有权

    公开(公告)号：US11258432B1

    公开(公告)日：2022-02-22

    申请号：US17125561

    申请日：2020-12-17

    Applicant: Silicon Laboratories Inc.

    Inventor： Péter Onódy ,  András V. Horváth

    IPC: H03K5/125 ,  H03K5/1252 ,  H03H11/06 ,  H03H11/26 ,  H03K3/012 ,  H03K17/687 ,  H03K19/20

    Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

    Power over Ethernet Powered Device Configured for Low Duty-Cycle Operation
    6.
    发明申请
    Power over Ethernet Powered Device Configured for Low Duty-Cycle Operation 审中-公开
    以太网供电设备配置为低占空比操作

    公开(公告)号：US20170012787A1

    公开(公告)日：2017-01-12

    申请号：US14791969

    申请日：2015-07-06

    Applicant: Silicon Laboratories Inc.

    Inventor： Vince András Horváth ,  Tamás Marozsák ,  Péter Onódy ,  John Gammel

    IPC: H04L12/10 ,  H02M3/04

    CPC classification number: H04L12/10 ,  H04L12/40045

    Abstract: In some embodiments, a powered device includes a powered device circuit, which may include a maintain power signature (MPS) circuit configured to compare a sense current to a reference current. In a first mode, the MPS circuit may be configured to automatically generate an MPS signal when the sense current is less than the reference current.

    Abstract translation: 在一些实施例中，供电设备包括供电设备电路，其可以包括被配置为将感测电流与参考电流进行比较的维持功率签名（MPS）电路。 在第一模式中，MPS电路可以被配置为当感测电流小于参考电流时自动生成MPS信号。

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