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    CONTROL OF THE POWER SUPPLY OVER A USB TYPE-C BUS
    312.
    发明申请
    CONTROL OF THE POWER SUPPLY OVER A USB TYPE-C BUS 审中-公开

    公开(公告)号：US20200310508A1

    公开(公告)日：2020-10-01

    申请号：US16809404

    申请日：2020-03-04

    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

    Inventor： Cedric FORCE ,  Thomas ALOFS ,  Christophe COCHARD ,  Olivier SCHULER

    IPC: G06F1/30 ,  G06F13/38 ,  G06F13/40

    Abstract: A power supply generates a power supply signal to provide electric power over a USB type-C bus. The power supply includes temperature sensing circuitry which senses indications of temperature of the power supply. Control circuitry coupled to the power supply circuitry and the temperature sensing circuitry compares indications of temperature sensed by the temperature sensing circuitry to three thresholds. The control circuitry determines a limit on available electric power provided by the power supply circuitry over the USB type-C bus based on the comparing. The limit on available electric power is set to one of three or more power levels based on the comparing.

    ARBITRATION DEVICE
    314.
    发明申请
    ARBITRATION DEVICE 审中-公开

    公开(公告)号：US20200225986A1

    公开(公告)日：2020-07-16

    申请号：US16739388

    申请日：2020-01-10

    Applicant: STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

    Inventor： Bruno DENIS ,  Christophe TABA

    IPC: G06F9/48 ,  G06F9/54 ,  G06F12/1081

    Abstract: Requests are received by a routing circuit. A plurality of first round-robin arbitration circuits are coupled to the routing circuit. There are as many first round-robin arbitration circuits as there are possible priority levels for the requests. The routing circuit operates to transmit each received request to a number of first round-robin arbitration circuits determined according to the priority level of the request. A second round-robin arbitration circuit has inputs respectively connected to the outputs of the first round-robin arbitration circuits.

    ELECTRONIC DEVICE COMPRISING AN ELECTRONIC CHIP PROVIDED WITH AN OPTICAL CABLE
    316.
    发明申请
    ELECTRONIC DEVICE COMPRISING AN ELECTRONIC CHIP PROVIDED WITH AN OPTICAL CABLE 审中-公开

    公开(公告)号：US20200174206A1

    公开(公告)日：2020-06-04

    申请号：US16701355

    申请日：2019-12-03

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Florian PERMINJAT ,  Romain COFFY ,  Jean-Michel RIVIERE

    IPC: G02B6/43 ,  H05K1/02

    Abstract: A carrier substrate includes a first network of electrical connections and recess. An electronic chip is mounted to the carrier substrate within the recess. The electronic chip includes an integrated guide of optical waves and a second network of electrical connections. A end section of an elongate optical cable is mounted on one side of the electronic chip with a longitudinal guide of optical waves optically coupled to the integrated guide of optical waves. Electrical connection elements are interposed between a face of the electronic chip and a bottom wall of the recess, such that first connect pads of the first electrical connection network are connected to second connect pads of the second electrical connection network through the electrical connection elements.

    Scan chain circuit supporting logic self test pattern injection during run time
    318.
    发明授权
    Scan chain circuit supporting logic self test pattern injection during run time 有权

    公开(公告)号：US10598728B2

    公开(公告)日：2020-03-24

    申请号：US15867285

    申请日：2018-01-10

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Bruno Fel

    IPC: G01R31/3177 ,  G01R31/3185

    Abstract: A scan chain for testing a combinatorial logic circuit includes a first scan chain path of flip-flops connected to the combinatorial logic circuit for functional mode operation during runtime of the combinatorial logic circuit. A second scan chain path of flip-flops is also connected to the combinatorial logic circuit and supports both a shift mode and a capture mode. The second scan chain path operates in shift mode while the first scan chain path is connected to the combinatorial logic circuit for functional mode operation. The second scan chain is then connected to the combinatorial logic circuit when run time is interrupted and operates in capture mode to apply the test data to the combinatorial logic circuit.

    DISTRIBUTED MICROCONTROLLER
    319.
    发明申请
    DISTRIBUTED MICROCONTROLLER 审中-公开

    公开(公告)号：US20200050579A1

    公开(公告)日：2020-02-13

    申请号：US16530069

    申请日：2019-08-02

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Giovanni Scozzola

    IPC: G06F15/78 ,  G06F13/42

    Abstract: A microcontroller includes distinct electronic functions and an interconnection circuit capable of transmitting in wireless fashion data between the functions. The microcontroller can be operated by writing configuration characteristics into a memory of the interconnection circuit for electronic functional circuits that do not have configuration characteristics contained in the memory and erasing configuration characteristics from the memory for electronic functional circuits that have configuration characteristics contained in the memory but are determined to not be able to wirelessly communicate with the interconnection circuit. Data can be wirelessly transmitted between the interconnection circuit and electronic functional circuits having configuration characteristics contained in the memory.

    Method and device for transfer of data to or from a memory
    320.
    发明授权
    Method and device for transfer of data to or from a memory 有权

    公开(公告)号：US10558587B2

    公开(公告)日：2020-02-11

    申请号：US15444558

    申请日：2017-02-28

    Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Grand Ouest) SAS

    Inventor： Abdelaziz Goulahsen ,  Patrice Derouet

    IPC: G06F12/14 ,  G06F21/60

    Abstract: A method for reading or writing data at an address of a memory is disclosed. The data includes a number of consecutive words that each has a plurality of bits. The words are transferred to or from the memory in synchronization with a clock signal so that each word is transferred in one cycle of the clock signal. The bits are scrambled or unscrambled by applying a logic function to the bits of each word. The logic function is identical for the scrambling and the unscrambling and makes use of a bit-key that is dedicated to the word and is identical for the scrambling and the unscrambling. Each bit-key comes from a pseudo-random series generated based on the address.

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