公开(公告)号：US20140241102A1

公开(公告)日：2014-08-28

申请号：US14271165

申请日：2014-05-06

Applicant: STMicroelectyronics International N.V. ,  STMicroelectronics, SA

Inventor： Nishu KOHLI ,  Robin M. WILSON

IPC: G11C8/18

CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

Abstract: A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Abstract translation: 存储器电路包括响应于内部时钟的第一边缘而可操作的存储器组件; 以及响应于系统时钟产生内部时钟的内部时钟产生电路，其中响应于系统时钟的上升沿和下降沿产生内部时钟的第一边缘。

公开(公告)号：US20140173544A1

公开(公告)日：2014-06-19

申请号：US14105382

申请日：2013-12-13

Applicant: STMicroelectronics SA ,  Commissariat a l'energie atomique et aux energies alternatives

Inventor： Bastien Giraud ,  Philippe Flatresse ,  Matthieu Le Boulaire ,  Jean-Philippe Noel

IPC: G06F17/50 ,  H01L21/84

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  H01L21/84

Abstract: An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.

Abstract translation: 包括排列成一排的第一和第二FDSOI UTBOX单元的IC，其中第一和第二FDSOI UTBOX单元排列成一行，其中第一和第二FOSOI UTBOX单元布置成具有和接地平面以上的nMOS晶体管和N型阱，以及配置有接地平面以上的铅垂和P 型井，N型阱和P型阱布置在行轴的任一侧，其中第二个包括防止天线效应的二极管或阱分接电池，第二电池包括P型阱 被布置成pMOS晶体管的P型阱的对准并且包括以nMOS晶体管的N型阱的排列方式布置的N型阱，第二单元包括耦合到其P型阱的金属连接 并且连接到具有N型井的高级金属连接元件排列的铅垂，金属连接在轴的任一侧延伸。

公开(公告)号：US20140153078A1

公开(公告)日：2014-06-05

申请号：US14084702

申请日：2013-11-20

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert MANOUVRIER

IPC: G02F1/015

CPC classification number: G02F1/015 ,  G02F1/025 ,  G02F1/2257

Abstract: A simulation model is for an optical modulator that may include an optical phase shifter in a semiconductor material structure between two sections of an optical waveguide. The semiconductor material structure may include one of a P-N and P-I-N junction in a plane parallel to an axis of the optical waveguide. The model may include a diode configured to characterize an electrical behavior of the one of the P-N and P-I-N junction such that a change in a global refractive index of the optical phase shifter is expressed, by a coefficient, based upon an amount of charges in the one of the P-N and P-I-N junctions and raised to a power. The coefficient and the power may be empirical values based upon the semiconductor material and a wavelength.

Abstract translation: 仿真模型用于可以包括在光波导的两个部分之间的半导体材料结构中的光学移相器的光学调制器。 半导体材料结构可以在平行于光波导的轴的平面中包括P-N和P-I-N结中的一个。 该模型可以包括被配置为表征PN和PIN结中的一个的电气行为的二极管，使得光学移相器的全局折射率的变化由系数表示，基于在 一个PN和PIN接口，并提高到一个权力。 系数和功率可以是基于半导体材料和波长的经验值。

公开(公告)号：US20140126647A1

公开(公告)日：2014-05-08

申请号：US14154057

申请日：2014-01-13

Applicant: STMICROELECTRONICS SA

Inventor： Marina NICOLAS

IPC: H04N19/51

CPC classification number: H04N19/00703 ,  H04N5/145 ,  H04N7/014 ,  H04N19/51 ,  H04N19/521 ,  H04N19/56

Abstract: A motion estimation method and device are provided for processing images to be inserted, between a preceding original image and a following original image, into a sequence of images. Each image is divided into pixel blocks associated with motion vectors. For a current block of an image being processed, motion vectors associated with blocks of the image being processed and/or associated with blocks of a processed image are selected. Candidate vectors are generated from selected motion vectors. An error is calculated for each candidate vector. A penalty is determined for a subset of candidate vectors on the basis of the values of the pixels of the pixel block in the preceding original image from which the candidate motion vector points to the current block and/or on the basis of the values of the pixels of the pixel block in the following original image to which the candidate motion vector points from the current block.

Abstract translation: 提供了一种运动估计方法和装置，用于将先前的原始图像和下一个原始图像之间插入的图像处理成图像序列。 每个图像被分成与运动矢量相关联的像素块。 对于正在处理的图像的当前块，选择与被处理图像的块正在处理和/或关联的图像的块相关联的运动矢量。 从选定的运动矢量生成候选向量。 为每个候选向量计算一个错误。 基于候选运动矢量指向当前块的前一原始图像中的像素块的像素值和/或基于当前块的值，确定候选矢量子集的惩罚 下一原始图像中的像素块的像素，候选运动矢量指向的当前块。

公开(公告)号：US20140089885A1

公开(公告)日：2014-03-27

申请号：US14028188

申请日：2013-09-16

Applicant: STMicroelectronics SA

Inventor： Julien Le Coz ,  Sylvain Engels ,  Alain Tournier

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/505 ,  G06F2217/84

Abstract: A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal propagation are also determined. A second assembly of control logic cells is provided which copies the first assembly in terms of number of cells, type of cells and cell connection such that each of the control cells is a homolog of a corresponding critical cell. Charge cells are provided at the outputs of the control cells having an equivalent capacitance in accordance with the determined capacitance of the output cells. For each control cell, logic levels are asserted in accordance with the determined configuration of the critical path. A signal generator applies a signal the input of the second assembly and a signal receiver is coupled to the output of the second assembly.

Abstract translation: 要监测关键电池的第一组装。 确定耦合到关键路径的输出单元的等效电容。 信号传播的关键单元的逻辑电平输入也被确定。 提供了控制逻辑单元的第二组件，其根据单元的数量，单元的类型和单元连接复制第一组件，使得每个控制单元是相应的关键单元的同源物。 根据所确定的输出单元的电容，在具有等效电容的控制单元的输出处提供充电单元。 对于每个控制单元，根据确定的关键路径的配置来确定逻辑电平。 信号发生器将信号施加到第二组件的输入端，信号接收器耦合到第二组件的输出。

公开(公告)号：US08654574B2

公开(公告)日：2014-02-18

申请号：US13791827

申请日：2013-03-08

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics SA ,  Medtronic, Inc.

Inventor： Kevin K. Walsh ,  Paul F. Gerrish ,  Larry E. Tyler ,  Mark A. Lysinger ,  David C. McClure ,  François Jacquet

IPC: G11C11/00

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C11/417

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract translation: 具有串联连接在每个存储单元的相应位存储节点之间的两个电容器的SRAM。 存储单元的两个反相器由正电压和低电压供电。 两个电容器在公共节点处彼此连接。 泄漏电流发生器耦合到公共节点。 泄漏电流发生器向公共节点提供泄漏电流，以保持大约在高和低SRAM电源的电压之间的一半的电压。

公开(公告)号：US20140032188A1

公开(公告)日：2014-01-30

申请号：US13949884

申请日：2013-07-24

Applicant: STMicroelectronics SA

Inventor： Jean-Robert Manouvrier

IPC: G06F17/10

CPC classification number: G06F17/10 ,  G06F17/5036

Abstract: The electric behavior of a reverse-biased PN junction diode is modeled by measuring the value of voltage V present across the diode and the value of the corresponding current I running through this diode, the voltage V varying within a range of values including the value of diode breakdown voltage. A representation of a function ln  ( I - I s ) according to voltage V is established from the measured values of current I and of voltage V, IS being the saturation current of the diode. A linear function representative of a substantially linear portion of the function, characterized by voltages V greater than breakdown voltage VBK in terms of absolute value, is determined. An avalanche multiplication factor MM is then calculated by MM = 1 +  ( - slbv · V + bv bv ) , with parameter slbv equal to the ordinate at the origin of the linear function, and parameter slbv/bv equal to the slope of the linear function.

Abstract translation: 反向偏置PN结二极管的电气行为通过测量二极管上存在的电压V的值和通过该二极管的相应电流I的值来建模，电压V在包括的值的范围内变化 二极管击穿电压。 根据电压I和电压V的测量值，IS是二极管的饱和电流建立函数ln（I-I s）的表示。 确定表示功能的基本线性部分的线性函数，其特征在于以绝对值计的大于击穿电压VBK的电压V。 然后通过MM = 1 +（ - slbv·V + bv bv）计算雪崩倍增因子MM，参数slbv等于线性函数原点的纵坐标，参数slbv / bv等于 线性函数。

公开(公告)号：US20140017871A1

公开(公告)日：2014-01-16

申请号：US13933396

申请日：2013-07-02

Applicant: STMicroelectronics SA ,  Commissariat a l'energie atomique et aux energies alternatives

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/66

CPC classification number: H01L29/66234 ,  H01L27/0259 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/78606

Abstract: An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well.

Abstract translation: 集成电路包括半导体衬底，硅层，布置在衬底和层之间的掩埋隔离层，包括具有第一掺杂的集电极和发射极的双极晶体管，以及具有第二掺杂的基极和基极触点， 基极与集电极和发射极，集电极，发射极，基极接触和基极共面形成结，阱具有第二掺杂和铅与集电极，发射极，基极接触和基极，阱分离集电极，发射极 和基底接触，具有第二掺杂并且在基底接触和基底之间延伸;隔离沟槽铅与基底并延伸超出该层但不到达发射极和集电极的底部;以及另一隔离沟槽， 基极接触，集电极和发射极，沟槽延伸超过掩埋层进入阱。

公开(公告)号：US20130271304A1

公开(公告)日：2013-10-17

申请号：US13914145

申请日：2013-06-10

Applicant: Centre National de Recherche Scientifique (CNRS) ,  STMicroelectronics SA

Inventor： Didier Belot ,  Jean-Baptiste Begueret ,  Yann Deval ,  Dominique Dallet ,  André Mariano

IPC: H03M3/00

CPC classification number: H03M3/458 ,  H03M3/402 ,  H03M3/484 ,  H03M3/50

Abstract: Continuous time analogue/digital converter, comprising a sigma delta modulator (MSD1) configured to receive an analogue input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD1).

Abstract translation: 连续时间模拟/数字转换器，包括被配置为接收模拟输入信号（x（t））并且包括其斩波频率等于采样的一半的高通滤波装置（MF）的Σ-Δ调制器（MSD1） 调制器（MSD1）的量化装置（QTZ）的频率（Fs）。

公开(公告)号：US20130270649A1

公开(公告)日：2013-10-17

申请号：US13859341

申请日：2013-04-09

Applicant: STMICROELECTRONICS SA

Inventor： Alain Chantre ,  Pascal Chevalier ,  Gregory Avenier

IPC: H01L29/73 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L27/1203 ,  H01L29/1004 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66265 ,  H01L29/73 ,  H01L29/7317 ,  H01L29/7322 ,  H01L29/7371

Abstract: A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.

Abstract translation: 一种制造双极晶体管的方法，包括以下步骤：形成半导体衬底的第一表面掺杂区，其半导体层在其上延伸有第一绝缘层; 在所述器件的表面处形成硅层和第二绝缘层的堆叠; 限定与所述堆叠交叉的沟槽和与所述第一掺杂区域相对的所述半导体层，以及所述第一绝缘层的所述暴露区域中的开口; 在开口中形成单晶硅区域; 在与所述半导体层和所述硅层的剩余区域接触的单晶硅区域的表面上形成硅 - 锗区域; 以及至少在所述沟槽的剩余空间中形成第二掺杂区域。