Method for increasing I/O performance in systems having an encryption co-processor
    311.
    发明申请
    Method for increasing I/O performance in systems having an encryption co-processor 有权
    在具有加密协处理器的系统中增加I / O性能的方法

    公开(公告)号:US20110138194A1

    公开(公告)日:2011-06-09

    申请号:US12660952

    申请日:2010-03-08

    Applicant: Kurt Godwin

    Inventor: Kurt Godwin

    CPC classification number: H04L9/00

    Abstract: A system and method for improving performance while transferring encrypted data in an input/output (I/O) operation are provided. The method includes receiving a block of data. The method also includes dividing the block of data into a plurality of sub-blocks of data. The method further includes performing a first operation on a first sub-block. The method also includes performing a second operation on a second sub-block at substantially the same time as performing the first operation on the first sub-block. The method still further includes reassembling the plurality of sub-blocks into the block of data.

    Abstract translation: 提供了一种用于在输入/输出(I / O)操作中传送加密数据时提高性能的系统和方法。 该方法包括接收数据块。 该方法还包括将数据块划分成多个数据子块。 该方法还包括对第一子块执行第一操作。 该方法还包括在与第一子块执行第一操作基本相同的时间对第二子块执行第二操作。 该方法还包括将多个子块重新组合到数据块中。

    Micro-fluidic structure
    312.
    发明授权
    Micro-fluidic structure 有权
    微流体结构

    公开(公告)号:US07928520B2

    公开(公告)日:2011-04-19

    申请号:US12686199

    申请日:2010-01-12

    CPC classification number: B81C1/00119 B81B2203/0315 B81C2201/0109

    Abstract: A microfabricated structure that includes a first layer of material on a substrate, and a second layer of material over the first layer that forms an encapsulated cavity, and a structural support layer added to the second layer. Openings can be formed in the cavity, and the cavities can be layered side by side, vertically stacked with interconnections via the openings, and a combination of both can be used to construct stacked arrays with interconnections throughout.

    Abstract translation: 一种微制造结构,其包括在基底上的第一层材料,以及在形成封装空腔的第一层上的第二材料层,以及添加到第二层的结构支撑层。 可以在空腔中形成开口,并且空腔可以并排堆叠,通过开口垂直地堆叠有互连,并且两者的组合可以用于构造整个具有互连的堆叠阵列。

    MODULAR LOW STRESS PACKAGE TECHNOLOGY
    313.
    发明申请
    MODULAR LOW STRESS PACKAGE TECHNOLOGY 有权
    模块式低应力包技术

    公开(公告)号:US20110086469A1

    公开(公告)日:2011-04-14

    申请号:US12903761

    申请日:2010-10-13

    Abstract: A method of manufacturing a protected package assembly: providing a protective modular package cover in accordance with a modular design; selectively applying an adhesive to the cross member of each subassembly receiving section of the protective modular package cover that will receive a subassembly to form an adhesive layer of the protective modular package cover; encapsulating the one or more subassemblies in the subassembly receiving sections on the selectively applied adhesive layer to generate a protected package assembly; and controlling application of a distributed downward clamping force applied to the top surfaces of the subassemblies received by the protective modular package cover and useful for mounting the protected package assembly to a core through activation of fastener elements and cross members of the subassembly receiving sections.

    Abstract translation: 一种制造受保护的封装组件的方法:根据模块化设计提供保护性模块化封装盖; 选择性地将粘合剂施加到保护性模块化封装盖的每个子组件接收部分的横向构件上,所述组件接收部分将接纳子组件以形成保护性模块化封装盖的粘合剂层; 将所述一个或多个子组件封装在所述选择性施加的粘合剂层上的子组件接收部分中,以产生受保护的封装组件; 以及控制施加到由所述保护性模块化封装盖接收的所述子组件的顶表面上的分布式向下夹持力的应用,并且用于通过激活所述子组件接收部分的紧固件元件和横向构件将所述受保护的封装组件安装到芯体。

    MODULAR LOW STRESS PACKAGE TECHNOLOGY
    314.
    发明申请
    MODULAR LOW STRESS PACKAGE TECHNOLOGY 有权
    模块式低应力包技术

    公开(公告)号:US20110084376A1

    公开(公告)日:2011-04-14

    申请号:US12903752

    申请日:2010-10-13

    Abstract: A protective modular package assembly with one or more subassemblies, each having a base element, a sidewall element coupled to the base element, and a semiconductor device disposed within and coupled to the sidewall element and the base element; a protective modular package cover having fastening sections located at opposing ends of the cover, torque elements disposed on the opposing ends and configured to fasten the cover to a core, and subassembly receiving sections disposed between the fastening sections with each subassembly receiving section operable to receive a subassembly and having a cross member along the underside of the cover; and an adhesive layer configured to affix subassemblies to respective subassembly receiving sections. The torque elements are configured to transfer a downward clamping force generated at the fastening elements to a top surface of the subassemblies via the cross member of each of the one or more subassembly receiving sections.

    Abstract translation: 一种具有一个或多个子组件的保护性模块化封装组件,每个子组件具有基座元件,耦合到所述基座元件的侧壁元件,以及设置在所述侧壁元件和所述基座元件内并联接到所述侧壁元件的基底元件的半导体器件; 保护性模块化封装盖,其具有位于盖的相对端处的紧固部分,设置在相对端部上并被配置为将盖子紧固到芯部的扭矩元件以及设置在紧固部分之间的子组件接收部分,每个子组件接收部分可操作以接收 子组件,并且沿着盖的下侧具有横向构件; 以及被配置为将子组件固定到相应的子组件接收部分的粘合剂层。 扭矩元件构造成经由一个或多个子组件接收部分中的每一个的横向构件将在紧固元件处产生的向下夹持力传递到子组件的顶表面。

    Mechanism to reduce lookup latency in a pipelined hardware implementation of a trie-based IP lookup algorithm
    315.
    发明授权
    Mechanism to reduce lookup latency in a pipelined hardware implementation of a trie-based IP lookup algorithm 有权
    减少基于Trie的IP查找算法的流水线硬件实现中的查找延迟的机制

    公开(公告)号:US07924839B2

    公开(公告)日:2011-04-12

    申请号:US10313395

    申请日:2002-12-06

    CPC classification number: G06F17/30985

    Abstract: A series of hardware pipeline units each processing a stride during prefix search operations on a multi-bit trie includes, within at least one pipeline unit other than the last pipeline unit, a mechanism for retiring search results from the respective pipeline unit rather than passing the search results through the remaining pipeline units. Early retirement may be triggered by either the absence of subsequent strides to be processed or completion (a miss or end node match) of the search, together with an absence of active search operations in subsequent pipeline units. The early retirement mechanism may be included in those pipeline units corresponding to a last stride for a maximum prefix length shorter than the pipeline (e.g., 20 or 32 bits rather than 64 bits), in pipeline units selected on some other basis, or in every pipeline unit. Worst-case and/or average latency for prefix search operations is reduced.

    Abstract translation: 在多位特务的前缀搜索操作期间,每个处理步幅的一系列硬件流水线单元包括在除了最后一个流水线单元之外的至少一个流水线单元内,用于从相应流水线单元退出搜索结果的机制, 搜索结果通过剩余的管道单位。 提前退休可能是由于缺少要处理或完成的后续步骤(遗漏或结束节点匹配)的搜索,以及后续流水线单元中没有主动搜索操作可能触发。 早期退休机制可以被包括在对应于最后一步的流水线单元中,其最大前缀长度短于流水线(例如,20位或32位,而不是64位),以某种其他方式选择的流水线单元 管道单元。 前缀搜索操作的最差情况和/或平均延迟减少。

    System and method for efficiently executing single program multiple data (SPMD) programs
    316.
    发明授权
    System and method for efficiently executing single program multiple data (SPMD) programs 有权
    有效执行单程序多数据(SPMD)程序的系统和方法

    公开(公告)号:US07904905B2

    公开(公告)日:2011-03-08

    申请号:US10714179

    申请日:2003-11-14

    Inventor: Stefano Cervini

    CPC classification number: G06F9/4843 G06F9/3851

    Abstract: A system and method is disclosed for efficiently executing single program multiple data (SPMD) programs in a microprocessor. A micro single instruction multiple data (SIMD) unit is located within the microprocessor. A job buffer that is coupled to the micro SIMD unit dynamically allocates tasks to the micro SIMD unit. The SPMD programs each comprise a plurality of input data streams having moderate diversification of control flows. The system executes each SPMD program once for each input data stream of the plurality of input data streams.

    Abstract translation: 公开了一种用于在微处理器中有效执行单程序多数据(SPMD)程序的系统和方法。 微单指令多数据(SIMD)单元位于微处理器内。 耦合到微SIMD单元的作业缓冲区动态地将任务分配给微型SIMD单元。 SPMD程序各自包括具有适度的控制流多样化的多个输入数据流。 系统对多个输入数据流的每个输入数据流执行一次SPMD程序。

    Integrated circuit and method for classification of electrical devices and short circuit protection
    317.
    发明授权
    Integrated circuit and method for classification of electrical devices and short circuit protection 有权
    集成电路和电气设备分类方法及短路保护

    公开(公告)号:US07904260B2

    公开(公告)日:2011-03-08

    申请号:US12039065

    申请日:2008-02-28

    CPC classification number: H02H3/12 Y10T307/549

    Abstract: An integrated circuit device and method for classifying electrical devices is disclosed. A reference current response of a plurality of electrical devices is determined and stored in a memory. Real-time current response of a specific electrical device is measured and stored in the memory. A processor compared the measured real-time current response of the specific electrical device to the reference current responses of the plurality of electrical devices. A classification of the electrical device is then made based on the comparison.

    Abstract translation: 公开了一种用于对电气设备进行分类的集成电路装置和方法。 确定多个电气设备的参考电流响应并将其存储在存储器中。 测量特定电气设备的实时电流响应并将其存储在存储器中。 处理器将特定电气设备的测量的实时电流响应与多个电气设备的参考电流响应相比较。 然后根据比较进行电气设备的分类。

    Enhanced 1-HOP dynamic frequency hopping communities
    318.
    发明授权
    Enhanced 1-HOP dynamic frequency hopping communities 有权
    增强型1-HOP动态跳频社区

    公开(公告)号:US07903718B2

    公开(公告)日:2011-03-08

    申请号:US11969676

    申请日:2008-01-04

    CPC classification number: H04B1/715 H04B1/7143 H04B2001/7154 H04W84/14

    Abstract: A Dynamic Frequency Hopping Community (DFH Community) is formed from a plurality of Wireless Regional Area Network (WRAN) cells wherein each of the plurality of WRAN cells within the DFH Community is a one-hop neighbor of the leader cell. The leader cell sets and distributes a hopping pattern for use among the WRAN cells based on, in part, the number of usable channels and whether a WRAN cell is shared by two groups in the DFH Community.

    Abstract translation: 动态跳频共同体(DFH Community)由多个无线区域网(WRAN)小区形成,其中DFH群内的多个WRAN小区中的每一个都是前导小区的一跳邻居。 领导单元基于部分可用信道的数量以及DFH小区中的两个组是否共享一个WRAN小区,在WRAN小区之间设置和分配跳频模式以供在WRAN小区之间使用。

    Method of inter-system coexistence and spectrum sharing for dynamic spectrum access networks-on-demand spectrum contention
    319.
    发明授权
    Method of inter-system coexistence and spectrum sharing for dynamic spectrum access networks-on-demand spectrum contention 有权
    动态频谱接入网络 - 按需频谱争用的系统间共存和频谱共享方法

    公开(公告)号:US07869400B2

    公开(公告)日:2011-01-11

    申请号:US11549890

    申请日:2006-10-16

    CPC classification number: H04W16/14 H04W28/24 H04W74/08

    Abstract: This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and more particularly to a method of addressing inter-systems (cells) coexistence and spectrum sharing. The described method of spectrum sharing, called On-Demand Spectrum Contention, integrates Dynamic Frequency Selection and Transmission Power Control with iterative on-demand spectrum contentions and provides fairness, adaptability, and efficiency of spectrum access for dynamic spectrum access systems using active inter-system coordination.

    Abstract translation: 本发明涉及动态频谱接入网络的基于认知无线电的无线通信,更具体地涉及一种寻址系统间(小区)共存和频谱共享的方法。 所描述的频谱共享方法称为按需频谱争用,将动态频率选择和传输功率控制与迭代按需频谱争用相结合,为动态频谱接入系统使用主动系统提供了频谱接入的公平性,适应性和效率 协调。

    WIRELESS MULTIMEDIA TRANSPORT METHOD AND APPARATUS
    320.
    发明申请
    WIRELESS MULTIMEDIA TRANSPORT METHOD AND APPARATUS 有权
    无线多媒体传输方法和设备

    公开(公告)号:US20100293287A1

    公开(公告)日:2010-11-18

    申请号:US12767429

    申请日:2010-04-26

    Inventor: Osamu Kobayashi

    CPC classification number: H04L65/4092 H04L65/602 H04L65/80

    Abstract: Apparatus and methods for wireless data transmission in a multimedia network are disclosed. Disclosed is a network having a source coupled to a sink using a virtual channel that includes a wireless communication channel. A source end of the system provides a packetizing data stream having a stream of payloads such that each payload is associated with its respective originating source stream. The system configured to encode the packetized data stream for wireless transport. A non-wireless source end of the system receives quality of service information from downstream. Thereby enabling adjustments to the source content and packetized data streams.

    Abstract translation: 公开了一种用于多媒体网络中的无线数据传输的装置和方法。 公开了一种网络,其具有使用包括无线通信信道的虚拟信道耦合到宿的源。 系统的源端提供具有有效载荷流的打包数据流,使得每个有效载荷与其相应的起始源流相关联。 该系统被配置为对用于无线传输的分组化数据流进行编码。 系统的非无线源端从下游接收服务质量信息。 从而能够调整源内容和打包数据流。

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