公开(公告)号：US07716455B2

公开(公告)日：2010-05-11

申请号：US11003248

申请日：2004-12-03

Applicant: Stefano Cervini

Inventor： Stefano Cervini

IPC: G06F9/00

CPC classification number: G06F9/3836 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/383

Abstract: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set. The invention is useful for arithmetic intensive applications, such as graphic processors.

Abstract translation: 高速处理器 处理器包括各自执行指令集的子集的终端。 在至少一个终端中，以由数据流确定的顺序执行指令。 说明将以页面方式加载到终端中。 当指令的操作数由另一个指令生成时，进行符号化。 当指令的操作数可用时，该指令是“就绪”指令。 在每个周期中选择一个就绪指令并执行。 为了允许在终端之间传输数据，每个终端设置有接收站，使得在一个终端中生成的数据可以被发送到另一终端，以用作该终端中的操作数。 在一个实施例中，一个终端是算术终端，执行诸如加法，乘法和除法之类的算术运算。 处理器具有第二终端，其包含用于执行指令集中的所有其他指令的功能逻辑。 本发明对于诸如图形处理器的算术密集型应用是有用的。

公开(公告)号：US20100241835A1

公开(公告)日：2010-09-23

申请号：US12748124

申请日：2010-03-26

Applicant: Stefano Cervini

Inventor： Stefano Cervini

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/383

Abstract: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set. The invention is useful for arithmetic intensive applications, such as graphic processors.

Abstract translation: 高速处理器 处理器包括各自执行指令集的子集的终端。 在至少一个终端中，以由数据流确定的顺序执行指令。 说明将以页面方式加载到终端中。 当指令的操作数由另一个指令生成时，进行符号化。 当指令的操作数可用时，该指令是“就绪”指令。 在每个周期中选择一个就绪指令并执行。 为了允许在终端之间传输数据，每个终端设置有接收站，使得在一个终端中生成的数据可以被发送到另一终端，以用作该终端中的操作数。 在一个实施例中，一个终端是算术终端，执行诸如加法，乘法和除法之类的算术运算。 处理器具有第二终端，其包含用于执行指令集中的所有其他指令的功能逻辑。 本发明对于诸如图形处理器的算术密集型应用是有用的。

公开(公告)号：US08239660B2

公开(公告)日：2012-08-07

申请号：US12748124

申请日：2010-03-26

Applicant: Stefano Cervini

Inventor： Stefano Cervini

IPC: G06F9/00

CPC classification number: G06F9/3836 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/383

Abstract: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set. The invention is useful for arithmetic intensive applications, such as graphic processors.

Abstract translation: 高速处理器 处理器包括各自执行指令集的子集的终端。 在至少一个终端中，以由数据流确定的顺序执行指令。 说明将以页面方式加载到终端中。 当指令的操作数由另一个指令生成时，进行符号化。 当指令的操作数可用时，该指令是“就绪”指令。 在每个周期中选择一个就绪指令并执行。 为了允许在终端之间传输数据，每个终端设置有接收站，使得在一个终端中生成的数据可以被发送到另一终端，以用作该终端中的操作数。 在一个实施例中，一个终端是算术终端，执行诸如加法，乘法和除法之类的算术运算。 处理器具有第二终端，其包含用于执行指令集中的所有其他指令的功能逻辑。 本发明对于诸如图形处理器的算术密集型应用是有用的。

公开(公告)号：US07904905B2

公开(公告)日：2011-03-08

申请号：US10714179

申请日：2003-11-14

Applicant: Stefano Cervini

Inventor： Stefano Cervini

IPC: G06F9/46 ,  G06F15/76 ,  G06F9/40

CPC classification number: G06F9/4843 ,  G06F9/3851

Abstract: A system and method is disclosed for efficiently executing single program multiple data (SPMD) programs in a microprocessor. A micro single instruction multiple data (SIMD) unit is located within the microprocessor. A job buffer that is coupled to the micro SIMD unit dynamically allocates tasks to the micro SIMD unit. The SPMD programs each comprise a plurality of input data streams having moderate diversification of control flows. The system executes each SPMD program once for each input data stream of the plurality of input data streams.

Abstract translation: 公开了一种用于在微处理器中有效执行单程序多数据（SPMD）程序的系统和方法。 微单指令多数据（SIMD）单元位于微处理器内。 耦合到微SIMD单元的作业缓冲区动态地将任务分配给微型SIMD单元。 SPMD程序各自包括具有适度的控制流多样化的多个输入数据流。 系统对多个输入数据流的每个输入数据流执行一次SPMD程序。

公开(公告)号：US20060149929A1

公开(公告)日：2006-07-06

申请号：US11003248

申请日：2004-12-03

Applicant: Stefano Cervini

Inventor： Stefano Cervini

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/383

Abstract: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set. The invention is useful for arithmetic intensive applications, such as graphic processors.

Abstract translation: 高速处理器 处理器包括各自执行指令集的子集的终端。 在至少一个终端中，以由数据流确定的顺序执行指令。 说明将以页面方式加载到终端中。 当指令的操作数由另一个指令生成时，进行符号化。 当指令的操作数可用时，该指令是“就绪”指令。 在每个周期中选择一个就绪指令并执行。 为了允许在终端之间传输数据，每个终端设置有接收站，使得在一个终端中生成的数据可以被发送到另一终端，以用作该终端中的操作数。 在一个实施例中，一个终端是算术终端，执行诸如加法，乘法和除法之类的算术运算。 处理器具有第二终端，其包含用于执行指令集中的所有其他指令的功能逻辑。 本发明对于诸如图形处理器的算术密集型应用是有用的。

公开(公告)号：US07103091B2

公开(公告)日：2006-09-05

申请号：US10141460

申请日：2002-05-07

Applicant: Stefano Cervini

Inventor： Stefano Cervini

IPC: H04B1/69 ,  H04B1/707 ,  H04B1/713

CPC classification number: H04B1/7115 ,  H04B2201/70707

Abstract: An architecture for a rake receiver of a CMDA demodulator utilizes a common data path for signal processing. This common data path is shared by all channels (either physical channels or propagation paths within physical channels) to avoid redundant calculations, reduce circuit space and reduce power consumption. The sharing of the common data path for demodulation is made on a time divided manner, with each channel being given sequential access to the data path to perform all or part of a given demodulation function (for example, de-scrambling, de-spreading, de-rotating, and de-skewing accumulation).

公开(公告)号：US07099293B2

公开(公告)日：2006-08-29

申请号：US10136650

申请日：2002-05-01

Applicant: Stefano Cervini

Inventor： Stefano Cervini

IPC: H04B7/216

CPC classification number: H04B1/7113 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11901 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A demodulator in a wireless communication network for combining symbols without the need to store the received symbols in buffers for subsequent retrieval and accumulation. The demodulator includes a plurality of accumulators capable of accumulating received symbols, each symbol associated with a physical channel and a propagation path. The demodulator includes a multiplexer for routing the received symbols to an appropriate accumulator selected from the plurality of accumulators. The symbols received from different propagation paths are each routed and accumulated to an appropriate accumulator based on a physical channel of the received symbol and a value of an indicator associated with a propagation path of the received symbol.

公开(公告)号：US20050108720A1

公开(公告)日：2005-05-19

申请号：US10714179

申请日：2003-11-14

Applicant: Stefano Cervini

Inventor： Stefano Cervini

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/4843 ,  G06F9/3851

Abstract: A system and method is disclosed for efficiently executing single program multiple data (SPMD) programs in a microprocessor. A micro single instruction multiple data (SIMD) unit is located within the microprocessor. A job buffer that is coupled to the micro SIMD unit dynamically allocates tasks to the micro SIMD unit. The SPMD programs each comprise a plurality of input data streams having moderate diversification of control flows. The system executes each SPMD program once for each input data stream of the plurality of input data streams.

Abstract translation: 公开了一种用于在微处理器中有效执行单程序多数据（SPMD）程序的系统和方法。 微单指令多数据（SIMD）单元位于微处理器内。 耦合到微SIMD单元的作业缓冲区动态地将任务分配给微型SIMD单元。 SPMD程序各自包括具有适度的控制流多样化的多个输入数据流。 系统对多个输入数据流的每个输入数据流执行一次SPMD程序。

公开(公告)号：US5862226A

公开(公告)日：1999-01-19

申请号：US798618

申请日：1997-02-11

Applicant: Stefano Cervini

Inventor： Stefano Cervini

IPC: H04H20/72 ,  H04H40/27 ,  H04L27/26 ,  H04H5/00

CPC classification number: H04H40/27 ,  H04L27/2647 ,  H04H20/72 ,  H04H2201/20

Abstract: The broadcast mode of the different ones set by the international standards for digital audio broadcasting (DAB) according to a coded orthogonal frequency division multiplexing scheme (COEFDM) may be automatically detected in a receiver through a detection routine. Many of the calculation modules required by the automatic mode detection system of the invention are already present in a receiver and can be exploited for performing the digital signal processing that leads to an automatic recognition of the broadcast mode of the station on which the receiver is tuned.

Abstract translation: 可以通过检测程序在接收机中自动检测根据编码正交频分复用方案（COEFDM）的数字音频广播（DAB）国际标准设定的不同播送模式。 本发明的自动模式检测系统所需的许多计算模块已经存在于接收机中，并且可以用于执行数字信号处理，这导致对其上调谐接收机的站的广播模式的自动识别 。