公开(公告)号：US06531710B1

公开(公告)日：2003-03-11

申请号：US09853342

申请日：2001-05-10

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2904

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2026 ,  H01L21/76264 ,  H01L21/76283

Abstract: An ULSI MOSFET formed using silicon on insulator (SOI) principles includes masking regions of an amorphous silicon film on a substrate and exposing intended active regions. Laser energy is directed against the intended active regions to anneal these regions without annealing the masked regions, thereby increasing production throughput and decreasing defect density.

Abstract translation: 使用绝缘体上硅（SOI）原理形成的ULSI MOSFET包括在衬底上的非晶硅膜的掩蔽区域并暴露预期的有源区域。 激光能量针对预期的有源区域进行退火以退火这些区域而不对掩蔽区域进行退火，由此增加生产量并降低缺陷密度。

公开(公告)号：US06528851B1

公开(公告)日：2003-03-04

申请号：US09871191

申请日：2001-05-31

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2701

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78621

Abstract: A semiconductor-on-insulator (SOI) transistor is disclosed. The SOI transistor includes a source region, a drain region and a body region disposed therebetween, the body region including a gate disposed thereon, the source and drain regions including respective silicide regions. The body region includes a region of recombination centers formed by atom implantation, wherein atoms forming the region of recombination centers are implanted at an angle from opposite sides of the gate in a direction towards the body region, with the gate and source and drain silicide regions acting as an implant blocking mask, such that the region of recombination centers is disposed between a source/body junction and a drain/body junction. Also disclosed is a method of fabricating the SOI transistor.

Abstract translation: 公开了一种绝缘体上半导体（SOI）晶体管。 SOI晶体管包括源极区域，漏极区域和设置在其间的体区域，所述体区域包括设置在其上的栅极，源区域和漏极区域包括各自的硅化物区域。 身体区域包括通过原子注入形成的复合中心区域，其中形成复合中心区域的原子沿着朝向身体区域的方向从栅极的相对侧以一定角度注入，栅极和源极和漏极硅化物区域 充当植入物阻挡掩模，使得复合中心区域设置在源极/主体结与漏极/主体结之间。 还公开了制造SOI晶体管的方法。

公开(公告)号：US06521501B1

公开(公告)日：2003-02-18

申请号：US09310170

申请日：1999-05-11

Applicant: Jeff Erhardt ,  Bin Yu ,  G. Jonathan Kluth

Inventor： Jeff Erhardt ,  Bin Yu ,  G. Jonathan Kluth

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/324 ,  H01L29/6659

Abstract: A method of forming a CMOS structure, the method including the acts of: forming a gate structure over a substrate layer; forming a silicide layer over the substrate layer; forming shallow source/drain areas in the substrate layer; forming an oxide diffusion barrier layer over the structure; forming a metal absorption layer over the oxide diffusion barrier layer; and melting portions of the substrate layer directly overlying the shallow source/drain areas, thereby transforming the shallow source/drain areas into shallow source/drain regions. The act of melting includes the act of exposing the metal absorption layer to pulsed laser beams.

Abstract translation: 一种形成CMOS结构的方法，所述方法包括以下动作：在衬底层上形成栅极结构; 在衬底层上形成硅化物层; 在衬底层中形成浅的源极/漏极区域; 在所述结构上形成氧化物扩散阻挡层; 在所述氧化物扩散阻挡层上形成金属吸收层; 并且将衬底层的部分直接覆盖在浅源极/漏极区域上，从而将浅的源极/漏极区域变换成浅的源极/漏极区域。 熔化的行为包括将金属吸收层暴露于脉冲激光束的行为。

公开(公告)号：US06518631B1

公开(公告)日：2003-02-11

申请号：US09824418

申请日：2001-04-02

Applicant: William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

Inventor： William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

IPC: H01L31113

CPC classification number: H01L29/6653 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a plurality of spacers used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract translation: 一种在绝缘体上半导体（SOI）衬底上形成的埋置氧化物（BOX）层的晶体管器件，以及设置在具有由隔离沟槽限定的有源区域的BOX层上的有源层。 该器件包括限定插入在SOI衬底的有源区域内形成的源极和漏极之间的沟道的栅极。 此外，该器件包括形成在源极和漏极上的多个薄硅化物层。 另外，多个薄硅化物层中的至少一个上硅化物层延伸超过下硅化物层。 此外，该装置还包括用于形成装置的多个间隔物。 该器件还包括形成在栅极的多晶硅电极上的第二多个薄硅化物层。

公开(公告)号：US06504214B1

公开(公告)日：2003-01-07

申请号：US10044246

申请日：2002-01-11

Applicant: Bin Yu ,  Qi Xiang

Inventor： Bin Yu ,  Qi Xiang

IPC: H01L2978

CPC classification number: H01L21/28194 ,  H01L21/2807 ,  H01L29/41783 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628

Abstract: A MOSFET device and method of fabrication. The MOSFET includes a gate having a gate electrode and a gate dielectric formed from a high-K material, the gate dielectric separating the gate electrode and a layer of semiconductor material. A source and a drain each formed by selective in-situ doped epitaxy and located adjacent opposite sides of the gate so as to define a body region from the layer of semiconductor material between the source and the drain and under the gate.

Abstract translation: 一种MOSFET器件及其制造方法。 MOSFET包括具有栅极电极和由高K材料形成的栅极电介质的栅极，栅极电介质分离栅电极和半导体材料层。 源极和漏极各自由选择性原位掺杂外延形成并且位于栅极的相邻相对侧，以便在源极和漏极之间以及在栅极之下限定半导体材料层的主体区域。

公开(公告)号：US06479868B1

公开(公告)日：2002-11-12

申请号：US09845659

申请日：2001-04-30

Applicant: Xilin Judy An ,  Bin Yu ,  Concetta E. Riccobene

Inventor： Xilin Judy An ,  Bin Yu ,  Concetta E. Riccobene

IPC: H01L2701

CPC classification number: H01L29/66772 ,  H01L29/78612 ,  H01L29/78624 ,  H01L29/78684

Abstract: A silicon-on-insulator (SOI) transistor. The SOI transistor includes a germanium implanted source and drain having a body disposed therebetween, and a gate disposed on the body, the germanium being implanted at an angle such that the source has a concentration of germanium at a source/body junction and the gate shields germanium implantation in the drain adjacent a drain/body junction resulting in a graduated drain/body junction. Also disclosed is a method of fabricating the SOI transistor.

Abstract translation: 绝缘体上硅（SOI）晶体管。 SOI晶体管包括锗注入源和漏极，其中设置有一个主体，以及设置在主体上的栅极，以一定角度注入锗，使得源在源极/主体结处具有锗的浓度，栅极屏蔽 在排水管/主体连接处的漏极中进行锗注入，导致刻度的漏极/体结。 还公开了制造SOI晶体管的方法。

公开(公告)号：US06472282B1

公开(公告)日：2002-10-29

申请号：US09639380

申请日：2000-08-15

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L29/7833

Abstract: A method of manufacturing an integrated circuit may include the steps of forming a deep amorphous region and doping the deep amorphous region. The doping of the deep amorphous region can form source and drain regions with extensions. After doping, the substrate is annealed. The annealing can occur at a low temperature. The deep amorphous region can be formed with a self-amorphizing implant.

Abstract translation: 制造集成电路的方法可以包括形成深非晶区域并掺杂深非晶区域的步骤。 深非晶区域的掺杂可以形成具有延伸的源极和漏极区域。 掺杂后，将基板退火。 退火可以在低温下进行。 深非晶区域可以用自身非晶化植入物形成。

公开(公告)号：US06465315B1

公开(公告)日：2002-10-15

申请号：US09476527

申请日：2000-01-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/1045 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586

Abstract: A method of fabricating an integrated circuit with a source side compensation implant utilizes tilt-angle implants. An asymmetric channel profile is formed in which less dopants are located on a source side. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 使用源极侧补偿注入制造集成电路的方法利用倾斜角植入。 形成非对称沟道轮廓，其中较少的掺杂剂位于源侧。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06455903B1

公开(公告)日：2002-09-24

申请号：US09491267

申请日：2000-01-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2976

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76283 ,  H01L29/0649

Abstract: An integrated circuit and method of fabricating integrated circuits is provided for an integrated circuit having threshold voltage adjustment. Unlike conventional methods and devices, threshold voltage adjustment is provided by an inert ion implantation process whereby inert ions are implanted into an underlying substrate. The implantation forms a semi-insulative layer comprised of an accumulation of inert ions. The inert ion region is formed between source and drain regions of a device on the integrated circuit. During operation of the device, the accumulation region confines the depth of the depletion layer. By confining the depth of the depletion layer, the threshold voltage of the device is reduced.

Abstract translation: 为具有阈值电压调整的集成电路提供集成电路和制造集成电路的方法。 与常规方法和装置不同，通过惰性离子注入工艺提供阈值电压调节，由此将惰性离子注入到下面的衬底中。 注入形成由惰性离子的积聚组成的半绝缘层。 惰性离子区域形成在集成电路上的器件的源极和漏极区域之间。 在装置运行期间，积聚区域限制耗尽层的深度。 通过限制耗尽层的深度，器件的阈值电压降低。

公开(公告)号：US06451644B1

公开(公告)日：2002-09-17

申请号：US09187618

申请日：1998-11-06

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L218234

CPC classification number: H01L21/2807 ,  H01L21/268 ,  H01L21/28052 ,  H01L21/28061 ,  H01L29/4916

Abstract: An ultra-large scale integrated (ULSI) circuit includes MOSFETs which have a gate conductor with dopants distributed in a box-like distribution. The dopants also achieve high electrical activation. The MOSFETs utilize gate structures with heavily doped polysilicon material or heavily doped polysilicon and germanium material. The polysilicon and polysilicon and germanium materials are manufactured by utilizing amorphous semiconductor layers. Excimer laser annealing is utilized to activate the dopants and to provide a box-like dopant profile.

Abstract translation: 超大规模集成（ULSI）电路包括具有分布在盒状分布中的掺杂剂的栅极导体的MOSFET。 掺杂剂也可实现高电活化。 MOSFET利用具有重掺杂多晶硅材料或重掺杂多晶硅和锗材料的栅极结构。 通过利用非晶半导体层制造多晶硅和多晶硅和锗材料。 使用准分子激光退火来激活掺杂剂并提供盒状掺杂物分布。